參數(shù)資料
型號: TTRN0110G
英文描述: ATM MULTIPLEXER|BGA|198PIN|CERAMIC
中文描述: ATM多路復(fù)用器|的BGA | 198PIN |陶瓷
文件頁數(shù): 25/30頁
文件大小: 578K
代理商: TTRN0110G
Agere Systems Inc.
25
Data Sheet
March 29, 2002
10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer
TTRN0110G
Timing Characteristics
(continued)
Transmit Timing
(continued)
The output 622 MHz clock and data signals are specified in Table 19.
Table 19. LVDS Input ac Timing Characteristics
Table 20. LVDS Output ac Timing Characteristics
Applicable
Pins
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
PICLKP/N
PICLKP/N
Duty Cycle
Clock Period
All signals differential
622 MHz
311 MHz
CLKMOD[1:0] = 00,
all signals differential
CLKMOD[1:0] = 00,
all signals differential
CLKMOD[1:0] = 10,
all signals differential
CLKMOD[1:0] = 10,
all signals differential
Any two package
inputs
40
0.07
50
1.6
3.2
60
%
ns
ns
ns
t
PERIOD
D[15:0]P/N
PICLKP/N
(622 MHz)
t
SU
Setup from Clock Edge to
D[15:0]P/N
Hold from Clock Edge to
D[15:0]P/N
Setup from Clock Edge to
D[15:0]P/N
Hold from Clock Edge to
D[15:0]P/N
Skew Tolerable at Receiver
Input to Meet Setup and
Hold Time Requirements
t
HOLD
0.07
ns
D[15:0]P/N
PICLKP/N
(311 MHz)
t
SU
0.68
ns
t
HOLD
0.78
ns
D[15:0]P/N
t
SKEW*
* Will be maintained for 100 mV < V
ID
< 400 mV throughout the receiver common-mode operating range.
200
ps
Applicable
Pins
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CK622P/N
CK155P/N
CK622P/N
CK155P/N
D[15:0]P/N
CK622P/N
*
Duty Cycle
All signals differential
40
50
60
%
t
PERIOD
Clock Period
100
100
250
1.6
6.4
–200
–400
350
520
260
260
400
400
70
500
ns
ns
ns
ns
ns
ns
ps
ps
ps
mV
* CLKMOD[1:0] = 01, all signals differential.
As defined in the
IEEE
standard 1596.3—1996.
t
SU
Setup from Clock Edge to
D[15:0]P/N
Hold from Clock Edge to
D[15:0]P/N
Rise Time, 20% to 80%
Fall Time, 20% to 80%
Differential Skew
Single Ended Output
Amplitude
9.95328 Gbits/s
10.70920 Gbits/s
9.95328 Gbits/s
10.70920 Gbits/s
Z
LOAD
= 100
± 1%
Z
LOAD
= 100
± 1%
t
HOLD
CK622P/N
CK155P/N
t
RISE
t
FALL
t
SKEW1
V
AMP
CK622P/N
CK155P/N
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