參數(shù)資料
型號(hào): TTRN0110G
英文描述: ATM MULTIPLEXER|BGA|198PIN|CERAMIC
中文描述: ATM多路復(fù)用器|的BGA | 198PIN |陶瓷
文件頁(yè)數(shù): 18/30頁(yè)
文件大?。?/td> 578K
代理商: TTRN0110G
18
Agere Systems Inc.
Data Sheet
March 29, 2002
10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer
TTRN0110G
CML Output Structure (Used on Outputs D10GP/N, CK10GP/N, LBDP/N)
The CML architecture is essentially a current-steering mechanism combined with an amplifier. This makes the
output swing of the signal a function of the termination resistor and the output current. The on-chip, 50
termination resistor provides a back termination and the output may be direct or ac-coupled to the load. For the
direct coupled case, the 50
load should be referenced to the positive 3.3 V supply, V
CCD
. This will ensure dc
levels that comply with the limits set.
2251(F)
Figure 7. Typical CML Output Structure
INPUT SIGNAL
50
RREFCML
V
CCD
I
OUT
X
ENABLE
+
V
REF
I
REF
DEVICE-INTERNAL CML OUTPUT BUFFER CIRCUIT
C
C
EXTERNAL OUTPUT TERMINATION
50
50
V
TT
V
TT
NOTE: SHOWN FOR ac COUPLING WHERE V
TT
MAY BE EITHER V
CCD
OR GND;
DIRECT COUPLING MAY ALSO BE USED,
BUT V
TT
MUST BE V
CCD
.
+
50
V
CCD
3 k
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