參數(shù)資料
型號： TTRN0110G
英文描述： ATM MULTIPLEXER|BGA|198PIN|CERAMIC
中文描述： ATM多路復用器|的BGA | 198PIN |陶瓷
文件頁數(shù)： 2/30頁
文件大小： 578K
代理商： TTRN0110G
Table of Contents
Contents
Page
2
Agere Systems Inc.
Data Sheet
March 29, 2002
10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer
TTRN0110G
Features ....................................................................................................................................................................1
Applications...............................................................................................................................................................1
Description.................................................................................................................................................................1
Block Diagram.........................................................................................................................................................3
Ball Information..........................................................................................................................................................4
Ball Diagram ...........................................................................................................................................................4
Ball Assignments ....................................................................................................................................................5
Ball Description.......................................................................................................................................................7
Functional Overview................................................................................................................................................11
Ethernet and FEC Rate Support..............................................................................................................................11
Clock Synthesizer Operation...................................................................................................................................11
Clock Synthesizer Loop Filter ...............................................................................................................................11
Clock Synthesizer Settling Time ...........................................................................................................................12
Loss of Lock Indicator (LCKLOSSN) ....................................................................................................................12
Clock Synthesizer Generated Jitter ......................................................................................................................12
Clock Synthesizer Jitter Transfer..........................................................................................................................13
Multiplexer Operation ..............................................................................................................................................14
10 GHz Clock Output Enable (ENCK10G)............................................................................................................14
Loopback 10 GHz Data Output (LBDP/N, ENLBDN)............................................................................................14
Reset (RESETN)...................................................................................................................................................14
Clocking Modes and Timing Adjustments ...............................................................................................................15
Forward Directional 622 Clocking Mode (CLKMOD[1:0] = 00, EXTCNTR, PICLKP/N, OVRFLW) ......................15
Forward Directional 311 Clocking Mode (CLKMOD[1:0] = 10, EXTCNTR, PICLKP/N, OVRFLW) ......................15
Contradirectional Clocking Mode (CLKMOD[1:0] = 01, PHADJ[1:0], EXTCNTR) ................................................16
Clockless Transfer Mode (CLKMOD[1:0]= 11, EXTCNTR) ..................................................................................17
CML Output Structure (Used on Balls D10GP/N, CK10GP/N, LBDP/N).................................................................18
Absolute Maximum Ratings.....................................................................................................................................19
Handling Precautions ..............................................................................................................................................19
Recommended Operating Conditions .....................................................................................................................19
Electrical Characteristics.........................................................................................................................................20
LVDS, CMOS, CML Inputs and Outputs...............................................................................................................20
Frequency Characteristics.......................................................................................................................................22
Reference Frequency (REFCLKP/N, REFFREQ) (Standard SONET Rate).........................................................22
Reference Frequency (REFCLKP/N, REFFREQ) (FEC Rate) .............................................................................22
Timing Characteristics.............................................................................................................................................23
Transmit Timing ....................................................................................................................................................23
Packaging Characteristics.......................................................................................................................................27
Package Crush Characteristics.............................................................................................................................27
CBGA Package Information..................................................................................................................................27
PWB Design Information.......................................................................................................................................27
Assembly Information ...........................................................................................................................................28
Reference Materials..............................................................................................................................................28
Package Diagram—198-Ball CBGA (Bottom View)..............................................................................................29
Ordering Information................................................................................................................................................30
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