參數(shù)資料
型號(hào)： TTRN0110G
英文描述： ATM MULTIPLEXER|BGA|198PIN|CERAMIC
中文描述： ATM多路復(fù)用器|的BGA | 198PIN |陶瓷
文件頁(yè)數(shù)： 11/30頁(yè)
文件大?。?/td> 578K
代理商： TTRN0110G
Agere Systems Inc.
11
Data Sheet
March 29, 2002
10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer
TTRN0110G
Functional Overview
The TTRN0110G performs the clock synthesis and
16:1 data multiplexing operations required to support
10 Gbits/s
1
OC-192/STM-64 applications compliant
with
Telcordia Technologies
and ITU standards.
Parallel 622 Mbits/s data is clocked into an input
register. Both forward directional and contradirectional
clocking modes are supported as well as a clockless
data transfer mode. The data is then multiplexed into a
10 Gbits/s serial stream and output buffered for
interfacing to a laser driver. A 10 GHz clock is
synthesized from a reference clock and is used to
retime the serial data. The 10 GHz clock is optionally
available as an output.
Ethernet and FEC Rate Support
The TTRN0110G will support both the normal OC-192/
STM-64 rate of 9.9532 GHz and the forward error
correction (FEC) rate of 10.7092 GHz. The FECN pin
selects the rate range at which the part is operated.
Throughout this document, the specifications are given
in terms of the normal operating rate only. All
frequency-based specifications are to be multiplied by
the appropriate scaling factor when not operating at the
OC-192/STM-64 rate. All time-based specifications,
with the exception of electrical signal rise and fall
times, are also to be multiplied by the appropriate
scaling factor. For example, a reference clock would
need to be applied at 167.33 MHz or 669.32 MHz (a
multiplication factor of 255/237), for the parallel data
interface to operate at 669.32 MHz when FECN = 0.
Clock Synthesizer Operation
The clock synthesizer uses a PLL to synthesize a
10 GHz clock from a reference frequency. A 622 MHz
clock derived from the 10 GHz synthesized clock may
be used to clock in the parallel data in contradirectional
clocking applications.
Clock Synthesizer Loop Filter
A typical loop filter that provides adequate damping for
less than 0.1 dB of jitter peaking is shown in Table 6.
Connect the filter components to LFP and LFN. The
component values can be varied to adjust the loop
dynamic response (see Table 6).
Table 6. Clock Synthesizer Loop Filter Component
Values
2249(F)
Figure 3. Clock Synthesizer Loop Filter
Components
1. The OC-192/STM-64 data rate of 9.95328 Gbits/s is typically
approximated as 10 Gbits/s in this document when referring to the
application rate. Similarly, the low-speed parallel interface data
rate of 622.08 Mbits/s is typically approximated as 622 Mbits/s.
The exact frequencies are used only when necessary for clarity.
Components
C1
*
C2, C3
R1
Values for 8 MHz Loop Bandwidth
0.15
μ
F ± 10%
~1 pF
3 k
± 5%
* Capacitor C1 should be either ceramic or nonpolar.
This value is the composite of any physical capacitance in
addition to any parasitic capacitance. These capacitors are
by default not populated.
C
3
C
2
C
1
R
1
LFN
LFP
V
CCA
V
CCA
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