參數(shù)資料
型號(hào)： TPS65735RSNR
廠商： TEXAS INSTRUMENTS INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQCC32
封裝： GREEN, PLASTIC, QFN-32
文件頁(yè)數(shù)： 32/32頁(yè)
文件大?。?/td> 1324K
代理商： TPS65735RSNR
SLVSAI6
– JUNE 2011
2.3
Thermal Information
TPS65735
THERMAL METRIC
RSN
UNITS
32 PINS
θJA
Junction-to-ambient thermal resistance(1)
38.9
θJCtop
Junction-to-case (top) thermal resistance(2)
26.5
θJB
Junction-to-board thermal resistance(3)
9.8
°C/W
ψJT
Junction-to-top characterization parameter(4)
0.3
ψJB
Junction-to-board characterization parameter(5)
9.8
θJCbot
Junction-to-case (bottom) thermal resistance(6)
3.5
(1)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2)
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3)
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4)
The junction-to-top characterization parameter,
ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(5)
The junction-to-board characterization parameter,
ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(6)
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
2.4
Quiescent Current
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IQ(SLEEP)
Power management core quiescent
@ 25
° C
8.6
10.5
A
current in sleep mode
VBAT = 3.6 V
VVIN = 0 V
No load on LDO
CHG_EN, BST_EN grounded
BST_FB = 300 mV
Power management core in sleep
mode / device
'off'
IQ(ACTIVE)
Power management core quiescent
@ 25
° C
39
53.5
A
current in active mode
VBAT = 3.6 V
VVIN = 0 V
Boost enabled but not switching,
H-bridge in grounded state
No load on LDO
Power management core in active
mode
2.5
Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BATTERY CHARGER POWER PATH
VUVLO(VIN)
Undervoltage lockout at power path
VVIN: 0 V → 4 V
3.2
3.3
3.45
V
input, VIN pin
VHYS-
Hysteresis on UVLO at power path
VVIN: 4 V → 0 V
200
300
mV
UVLO(VIN)
input, VIN pin
VIN-DT
Input power detection threshold
Input power detected if: (VVIN > VBAT
40
140
mV
+ VIN-DT);
VBAT = 3.6 V
VVIN: 3.5 V → 4 V
VHYS-INDT
Hysteresis on VIN-DT
VBAT = 3.6 V
20
mV
VVIN: 4 V → 3.5 V
Copyright
2011, Texas Instruments Incorporated
POWER MANAGEMENT CORE
9
Product Folder Link(s): TPS65735
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