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參數(shù)資料
| 型號： | TPS65735RSNR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQCC32 |
| 封裝： | GREEN, PLASTIC, QFN-32 |
| 文件頁數(shù)： | 10/32頁 |
| 文件大?。?/td> | 1324K |
| 代理商： | TPS65735RSNR |
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SLVSAI6
– JUNE 2011
During the fast charge phase, the following events may increase the timer durations:
1. The system load current activates the DPM loop which reduces the available charging current
2. The input current is reduced because the input voltage has fallen to VIN(LOW)
3. The device has entered thermal regulation because the IC junction temperature has exceeded TJ(REG)
During each of these events, the internal timers are slowed down proportionately to the reduction in
charging current.
If the pre-charge timer expires before the battery voltage reaches VLOWV, the charger indicates a fault
condition.
2.7.3
Charger Status (nCHG_STAT Pin)
The nCHG_STAT pin is used to indicate the charger status by an externally connected resistor and LED
circuit. The pin is an open drain input and the internal switch is controlled by the logic inside of the
charger. This pin may also be connected to a GPIO of the system MCU to indicate charging status. The
table below details the status of the nCHG_STAT pin for various operating states of the charger.
Table 2-1. nCHG_STAT Functionality
Charging Status
nCHG_STAT FET / LED
Pre-charge / Fast Charge / Charge Termination
ON
Recharge
OFF
OVP
OFF
SLEEP
OFF
2.8
LDO Operation
The power management core has a low dropout linear regulator (LDO) with variable output voltage
capability. This LDO is used for supplying the microcontroller and may be used to supply either an
external IR or RF module, depending on system requirements. The LDO can supply a continuous current
of up to 30 mA.
The output voltage (VVLDO) of the LDO is set by the state of the VLDO_SET pin. See Table 2-2 for details
on setting the LDO output voltage.
Table 2-2. VLDO_SET Functionality
VLDO_SET State
VLDO Output Voltage (VVLDO)
Low (VLDO_SET
< VIL(PMIC))
2.2 V
High (VLDO_SET
> VIH(PMIC))
3.0 V
2.8.1
LDO Internal Current Limit
The internal current limit feature helps to protect the LDO regulator during fault conditions. During current
limit, the output sources a fixed amount of current that is defined in the electrical specification table. The
voltage on the output in this stage can not be regulated and will be VOUT = ILIMIT × RLOAD. The pass
transistor integrated into the LDO will dissipate power, (VIN - VOUT) × ILIMIT, until the device enters thermal
shutdown. In thermal shutdown the device will enter the "SLEEP / POWER OFF" state which means that
the LDO will then be disabled and shut off.
18
POWER MANAGEMENT CORE
Copyright
2011, Texas Instruments Incorporated
Product Folder Link(s): TPS65735
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