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I
=
PFMDCDC1 enter
I
=
PFMDCDC2 enter
I
=
PFMDCDC3 enter
VINDCDC1
VINDCDC2
VINDCDC3
24
W
26
W
39
W
(1)
I
=
PFMDCDC1 leave
I
=
PFMDCDC2 leave
I
=
PFMDCDC3 leave
VINDCDC1
VINDCDC2
VINDCDC3
18
W
20
W
29
W
(2)
LOW RIPPLE MODE
Setting Bit 3 in register CON-CTRL to 1 enables the low ripple mode for all of the dc-dc converters if operated in
PFM mode. For an output current less than approximately 10 mA, the output voltage ripple in PFM mode is
reduced, depending on the actual load current. The lower the actual output current on the converter, the lower
the output ripple voltage. For an output current above 10 mA, there is only minor difference in output voltage
ripple between PFM mode and low ripple PFM mode. As this feature also increases switching frequency, it is
used to keep the switching frequency above the audible range in PFM mode down to a low output current.
SOFT START
Each of the three converters has an internal soft start circuit that limits the inrush current during start-up. The soft
start is realized by using a very low current to initially charge the internal compensation capacitor. The soft start
time is typically 750
μ
s if the output voltage ramps from 5% to 95% of the final target value. If the output is
already precharged to some voltage when the converter is enabled, then this time is reduced proportionally.
There is a short delay of typically 170
μ
s between the converter being enabled and switching activity actually
starting. This is to allow the converter to bias itself properly, to recognize if the output is precharged, and if so to
prevent discharging of the output while the internal soft start ramp catches up with the output voltage.
TPS65020
SLVS607–SEPTEMBER 2005
DETAILED DESCRIPTION (continued)
During the PSM the output voltage is monitored with a comparator, and by maximum skip burst width. As the
output voltage falls below the threshold, set to the nominal V
O
, the P-channel switch turns on and the converter
effectively delivers a constant current defined as follows.
If the load is below the delivered current then the output voltage rises until the same threshold is crossed in the
other direction. All switching activity ceases, reducing the quiescent current to a minimum until the output voltage
has dropped below the threshold again. If the load current is greater than the delivered current, then the output
voltage falls until it crosses the COMP LOW threshold, set to 2% below nominal V
O
, or the skip burst exceeds
16
×
1/switching frequency. Power Save Mode is exited and the converter returns to PWM mode.
These control methods reduce the quiescent current to typically 14
μ
A per converter, and the switching activity to
a minimum, thus achieving the highest converter efficiency. Setting the comparator thresholds at the nominal
output voltage at light load current results in a low output voltage ripple. The ripple depends on the comparator
delay and the size of the output capacitor. Increasing capacitor values makes the output ripple tend to zero. The
PSM is disabled through the I
2
C interface to force the individual converters to stay in fixed frequency PWM
mode.
22