參數(shù)資料
型號: TPS65020RHA
廠商: Texas Instruments, Inc.
英文描述: POWER MANAGEMENT IC FOR LI-ION POWERED SYSTEMS
中文描述: 電源管理IC鋰離子供電系統(tǒng)
文件頁數(shù): 11/44頁
文件大?。?/td> 3085K
代理商: TPS65020RHA
www.ti.com
TPS65020
SLVS607–SEPTEMBER 2005
TERMINAL FUNCTIONS (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Input signal indicating default VDCDC1 voltage, 0 = 3 V, 1 = 3.3 V This pin can also be connected to
a resistor divider between VDCDC1 and GND. If the output voltage of the DCDC1 converter is set in
a range from 0.6 V to VINDCDC1 V
Input signal indicating default VDCDC2 voltage, 0 = 1.8 V, 1 = 2.5 V This pin can also be connected
to a resistor divider between VDCDC2 and GND. If the output voltage of the DCDC2 converter is set
in a range from 0.6 V to VINDCDC2 V
Input signal indicating default VDCDC3 voltage, 0 = 1.3 V, 1 = 1.55 V This pin can also be connected
to a resistor divider between VDCDC3 and GND. If the output voltage of the DCDC3 converter is set
in a range from 0.6 V to VINDCDC3 V
VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator.
VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator.
VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator.
DEFDCDC1
10
I
DEFDCDC2
32
I
DEFDCDC3
1
I
DCDC1_EN
DCDC2_EN
DCDC3_EN
LDO REGULATOR SECTION
VINLDO
VLDO1
VLDO2
LDO_EN
VBACKUP
VRTC
VSYSIN
CONTROL AND I
2
C SECTION
HOT_RESET
TRESPWRON
RESPWRON
PWRFAIL
LOW_BAT
INT
SCLK
SDAT
PWRFAIL_SNS
LOWBAT_SNS
PB_IN
PB_OUT
25
24
23
I
I
I
19
20
18
22
15
16
14
I
I Input voltage for LDO1 and LDO2
Output voltage of LDO1
Output voltage of LDO2
Enable input for LDO1 and LDO2. Logic high enables the LDOs, logic low disables the LDOs
Connect the backup battery to this input pin.
Output voltage of the LDO/switch for the real time clock
Input of system voltage for VRTC switch
O
O
I
I
O
I
11
26
27
31
21
28
30
29
38
39
12
13
I
I
Push button input used to reboot or wake-up processor via RESPWRON output pin
Connect the timing capacitor to this pin to set the reset delay time: 1 nF
100 ms
Open drain System reset output
Open drain output. Active low when PWRFAIL comparator indicates low VBAT condition.
Open drain output of LOW_BAT comparator
Open drain output
Serial interface clock line
Serial interface data/address
Input for the comparator driving the PWRFAIL output
Input for the comparator driving the LOW_BAT output
Push button input debounced and output fed to latch at PB_OUT
Open drain output of latch driven by PB_IN. Low after power up.
O
O
O
O
I
I/O
I
I
I/O
I/O
11
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