參數(shù)資料
型號: TPA5051_07
廠商: Texas Instruments, Inc.
英文描述: FOUR CHANNEL DIGITAL AUDIO LIP-SYNC DELAY WITH I2C CONTROL
中文描述: 四通道數(shù)字音頻口形同步延遲與I2C控制
文件頁數(shù): 9/21頁
文件大?。?/td> 710K
代理商: TPA5051_07
www.ti.com
A6
A5
A0
R/W ACK A7
A6
A5
A4
A0 ACK
A6
A5
A0
ACK
Start
Condition
Stop
Condition
Acknowledge
Acknowledge
Acknowledge
I
2
C Device Address and
Read/Write Bit
Register
Data Byte
D7
D6
D1
D0 ACK
I
2
C Device Address and
Read/Write Bit
Not
Acknowledge
R/W
A1
A1
Repeat Start
Condition
MULTIPLE-BYTE READ
A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes
are transmitted by the TPA5051 to the master device as shown in
Figure 9
. With the exception of the last data
byte, the master device responds with an acknowledge bit after receiving each data byte.
A6
A0
ACK
Acknowledge
I
2
C Device Address and
Read/Write Bit
R/W
A6
A0
R/W ACK
A0
ACK
D7
D0
ACK
Start
Condition
Stop
Condition
Acknowledge
Acknowledge
Acknowledge
Last Data Byte
ACK
First Data Byte
Repeat Start
Condition
Not
Acknowledge
I
2
C Device Address and
Read/Write Bit
Register
Other Data Bytes
A7
A6
A5
D7
D0
ACK
Acknowledge
D7
D0
TPA5051 Operation
The following sections describe the registers configurable via I
2
C commands for the TPA5051.
Only a single decoupling capacitor (0.1
μ
F–1
μ
F) is required across VDD and GND. The ADDx terminals can be
directly connected to VDD or GND.
Table 1
describes the I
2
C addresses selectable via the ADDx terminals. A
schematic implementation of the TPA5051 is shown in
Figure 10
.
VDD
DATA1
LRCLK1
BCLK1
GND
DATA_OUT1
SDA
SCL
ADD0
ADD1
ADD2
GND
3.3 V
0.1 F
Digital Audio1
Word Clock1
Bit Clock1
Delayed Audio1
I C Clock
I C Data
I C Address
Select
Digital Audio2
Word Clock2
Bit Clock2
DATA2
LRCLK2
BCLK2
DATA_OUT2
Delayed Audio2
TPA5051
SLOS497A–JUNE 2006–REVISED JULY 2006
Figure 8. Single-Byte Read Transfer
Figure 9. Multiple-Byte Read Transfer
Figure 10. TPA5051 Schematic
9
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