參數(shù)資料
型號(hào): TPA5051_07
廠商: Texas Instruments, Inc.
英文描述: FOUR CHANNEL DIGITAL AUDIO LIP-SYNC DELAY WITH I2C CONTROL
中文描述: 四通道數(shù)字音頻口形同步延遲與I2C控制
文件頁數(shù): 13/21頁
文件大?。?/td> 710K
代理商: TPA5051_07
www.ti.com
I
2
C Examples
The following are some examples of I
2
C commands used to read or write to the TPA5051. For all conditions,
assume the address of the TPA5051 is set to 001.
Single Byte Write
In this example, the TPA5051 is set to mute both left and right channels of DATA1, and to operate in I
2
S mode.
D2
Start
ACK
01
ACK
C0
ACK
Stop
TPA5051 Address and
Write
Register Address
Data
Multiple Byte Write
D2
Start
ACK
01
00
04
ACK
TPA5051 Address and
Write
Register Address
(Control Register
DATA1
)
Data
(Right Delay Upper Bits
DATA1
)
ACK
ACK
00
ACK
Data
(Control Register
DATA1
)
Data
(Right Delay Lower Bits
DATA1
)
08
ACK
00
00
00
ACK
Data
(Left Delay Upper Bits
DATA1
)
Data
(RJ Packet = 0 Bits
DATA1
)
ACK
ACK
01
ACK
Data
(Frame Delay
DATA1
)
Data
(Complete Update
DATA1
)
Data
(Left Delay Lower Bits
DATA1
)
Stop
10
ACK
00
00
00
ACK
Data
(Control Register
DATA2
)
Data
(Left Delay Upper Bits
DATA2
)
ACK
ACK
00
ACK
Data
(Right Delay Lower Bits
DATA2
)
Data
(Left Delay Lower Bits
DATA2
)
Data
(Right Delay Upper Bits
DATA2
)
91
ACK
10
01
ACK
Data
(Frame Delay
DATA2
)
ACK
Data
(Complete Update
DATA2
)
Data
(RJ Packet = 16 Bits
DATA2
)
TPA5051
SLOS497A–JUNE 2006–REVISED JULY 2006
NOTE:
Because no complete update command was issued in this example, the stream type
change will not take effect until a
1
is written to the
Complete Update
register.
In this example, the TPA5051 is set to make both the left and right channels of both DATA1 and DATA2 active.
DATA1 is set to operate in I
2
S mode, delay the right channel by 1024 samples, and delay the left channel by
2048 samples. DATA2 is set to operate in the Right-Justified mode with a packet length of 16 bits. It is to delay
the audio signal by 40 ms using the Frame Delay function. Assume the audio sample rate (fs) = 48 kHz, and the
Frame rate = 50 Hz. This is a sequential write, so all registers must have data written to them.
13
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