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參數(shù)資料
| 型號： | TPA5051_07 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | FOUR CHANNEL DIGITAL AUDIO LIP-SYNC DELAY WITH I2C CONTROL |
| 中文描述： | 四通道數(shù)字音頻口形同步延遲與I2C控制 |
| 文件頁數(shù)： | 5/21頁 |
| 文件大?。?/td> | 710K |
| 代理商： | TPA5051_07 |
www.ti.com
Serial Audio Input Ports
over recommended operating conditions (unless otherwise noted)
th1
tsu1
tsu2
th2
DATA
BCLK
(Input)
LRCLK
(Input)
APPLICATION INFORMATION
AUDIO SERIAL INTERFACE
The audio serial interface for the TPA5051 consists of two 3-wire synchronous serial ports. Each includes an
LRCLK, BCLK, and DATA. BCLK is the serial audio bit clock, and it is used to clock the serial data present on
the DATA line into the serial shift register of the audio interface. Serial data is clocked into the TPA5051 on the
rising edge of BCLK. LRCLK is the serial audio left/right word clock, operated at the sampling frequency, fs. It is
used to latch serial data into the internal registers of the serial audio interface. BCLK can be operated at 32 to
64 times the sampling frequency for right-justified, left-justified, and I
2
S formats. Generally, both LRCLK and
BCLK should be synchronous to the system clock. However, the TPA5051 does not have a system clock, so the
only synchonization necessary is between BCLK and LRCLK.
AUDIO DATA FORMATS AND TIMING
The TPA5051 supports industry-standard audio data formats, including right-justified, I
2
S, and left-justified. The
data formats are shown in
Figure 4
. Data formats are selected using the I
2
C interface and register map (see
Table 1
).
TPA5051
SLOS497A–JUNE 2006–REVISED JULY 2006
PARAMETER
TEST CONDITIONS
MIN
1.024
TYP
MAX
12.288
UNIT
MHz
ns
ns
ns
ns
kHz
f
SCLKIN
Frequency, BCLK 32
×
fs, 48
×
fs, 64
×
fs
t
su1
Setup time, LRCLK to BCLK rising edge
t
h1
Hold time, LRCLK from BCLK rising edge
t
su2
Setup time, DATA to BCLK rising edge
t
h2
Hold time, DATA from BCLK rising edge
LRCLK frequency
BCLK duty cycle
LRCLK duty cycle
BCLK rising edges between LRCLK rising edges
10
10
10
10
32
48
192
50%
50%
LRCLK duty cycle = 50%
32
64
BCLK edges
Figure 3. Serial Data Interface Timing
5
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| TPA5051EVM | 功能描述:音頻 IC 開發(fā)工具 AUD DELAY DEVICE RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| TPA5051RSAR | 功能描述:音頻 DSP 4Ch Dig Aud Delay Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| TPA5051RSARG4 | 功能描述:音頻 DSP 4Ch Dig Aud Delay Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| TPA5051RSAT | 功能描述:音頻 DSP 4Ch Dig Aud Delay Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| TPA5051RSATG4 | 功能描述:音頻 DSP 4Ch Dig Aud Delay Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
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