參數(shù)資料
型號(hào)： TPA5051_07
廠商： Texas Instruments, Inc.
英文描述： FOUR CHANNEL DIGITAL AUDIO LIP-SYNC DELAY WITH I2C CONTROL
中文描述： 四通道數(shù)字音頻口形同步延遲與I2C控制
文件頁(yè)數(shù)： 10/21頁(yè)
文件大?。?/td> 710K
代理商： TPA5051_07
www.ti.com
SERIAL CONTROL INTERFACE REGISTER SUMMARY
CONTROL REGISTER (0x01, 0x09)
The control register allows the user to mute a specific audio channel. It is also used to specify the data type (I
2
S,
Right-Justified, or Left-Justified).
AUDIO DELAY REGISTERS (0x02–0x05, 0x0A–0x0D)
The audio delay for the left and right channels is fixed by writing a total of 13 bits (2 byte transfer) to upper and
lower registers as specified in
Table 1
. A multiple byte transfer should be performed starting with the control
register and following with 4 bytes to fill the upper and lower registers associated with right/left channel delay.
The decimal value of D0–D13 equals the number of samples to delay. The maximum number of delayed
samples per channel is 4095 for the TPA5051. This equates to 85.3 ms ([4095
×
(1/Fs)] at 48 kHz) of delay per
channel.
TPA5051
SLOS497A–JUNE 2006–REVISED JULY 2006
Table 2. Serial Control Register Summary
REGISTER
REGISTER NAME
NO. OF
BYTES
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CONTENTS
INITIALIZATION
VALUE
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0x01
(1)
0x02
(1)
0x03
(1)
0x04
(1)
0x05
(1)
0x06
(1)
0x07
(1)
0x08
(1)
0x09
(2)
0x0A
(2)
0x0B
(2)
0x0C
(2)
0x0D
(2)
0x0E
(2)
0x0F
(2)
0x10
(2)
Control Register
Right Delay Upper (5 bits)
Right Delay Lower (8 bits)
Left Delay Upper (5 bits)
Left Delay Lower (8 bits)
Frame Delay
RJ Packet Length
Complete Update
Control Register
Right Delay Upper (5 bits)
Right Delay Lower (8 bits)
Left Delay Upper (5 bits)
Left Delay Lower (8 bits)
Frame Delay
RJ Packet Length
Complete Update
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
(1)
(2)
I
2
C registers for serial data channel 1
I
2
C registers for serial data channel 2
Table 3. Control Registers (0x01, 0x09)
(1)
D7
0
0
1
1
–
–
–
–
D6
0
1
0
1
–
–
–
–
D5
X
X
X
X
X
X
X
X
D4
X
X
X
X
X
X
X
X
D3
X
X
X
X
X
X
X
X
D2
X
X
X
X
X
X
X
X
D1
–
–
–
–
0
0
1
1
D0
–
–
–
–
0
1
0
1
FUNCTION
Left and Right channel are active.
Left channel is MUTED.
Right channel is MUTED.
Left and Right channel are MUTED.
I
2
S data format
Right-justified data format (see PACKET LENGTH register 0x07)
Left-justified data format
Bypass mode – data is passed straight through without delay.
(1)
Default values are in
bold
.
10
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參數(shù)描述
TPA5051EVM 功能描述:音頻 IC 開發(fā)工具 AUD DELAY DEVICE RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評(píng)估:TAS5614L 工作電源電壓:12 V to 38 V
TPA5051RSAR 功能描述:音頻 DSP 4Ch Dig Aud Delay Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube
TPA5051RSARG4 功能描述:音頻 DSP 4Ch Dig Aud Delay Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube
TPA5051RSAT 功能描述:音頻 DSP 4Ch Dig Aud Delay Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube
TPA5051RSATG4 功能描述:音頻 DSP 4Ch Dig Aud Delay Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube
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