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參數(shù)資料
| 型號(hào)： | TP11362AN |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | CONNECTOR ACCESSORY |
| 中文描述： | A/MU-LAW, ADPCM CODEC, PDIP24 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-24 |
| 文件頁(yè)數(shù)： | 9/16頁(yè) |
| 文件大?。?/td> | 442K |
| 代理商： | TP11362AN |
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Functional Description
(Continued)
G.726. At power up, the outputs TSO and RSO are in
TRI-STATE mode. This “cold” reset process is asynchronous
and takes approximately 2000 CLK cycles for the initializa-
tion. During the reset process, the outputs TSO and RSO are
in TRI-STATE mode.
CHANNEL NOP
Each channel can be independently disabled. When EN is at
logic low on the falling edge of CE, the ADPCM transcoder
processing for that channel is disabled. The processor re-
quires 4 CLK cycles for CE to maintain all channel variables.
The data output ports are also placed in known states. After
this the processor waits for the next interrupt. Power is con-
served during this time by disabling the internal registers.
TSO outputs the following data after a channel NOP:
TABLE 6. TSO at Channel NOP
QSEL1
0
0
1
1
QSEL0
0
1
0
1
Mode
32 kbps
24 kbps
16 kbps
40 kbps
TSO
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0 0
The data pattern at TSO in Table 6 are shown with 3 ASCK
rising edges within the CE high pulse for the 32, 24, 16 kbps
modes and 4ASCK rising edges within the CE high pulse for
the 40 kbps mode (the MSB is shifted out with the falling
edge of CE). In the idle case (NOP) where EN is low at the
falling edge of CE, the TSO output is low for the duration of
the high CE pulse.
In the idle state (NOP), RSO outputs the following data (bit
representation with the sign-bit on the left followed by the
MSB, the sign-bit is the first bit after the rising edge of CE):
TABLE 7. RSO at Channel NOP
PCM1
0
1
Mode
8-Bit μ-Law
8-Bit A-Law
RSO
1 1 1 1 1 1 1 1
1 1 0 1 0 1 0 1
9
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TP11362AV | 制造商:Texas Instruments 功能描述: |
| TP11362AV/NOPB | 功能描述:IC PROCESSOR QUAD DIF PCM 28PLCC RoHS:是 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
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| TP11368N | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Octal Adaptive Differential PCM Processor |
| TP11368V | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
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