參數(shù)資料
型號: TP11362AN
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 編解碼器
英文描述: CONNECTOR ACCESSORY
中文描述: A/MU-LAW, ADPCM CODEC, PDIP24
封裝: 0.600 INCH, PLASTIC, DIP-24
文件頁數(shù): 11/16頁
文件大?。?/td> 442K
代理商: TP11362AN
Timing Specifications
(Continued)
Unless otherwise noted, limits printed in
bold
characters are guaranteed for V
= 5.0V
±
5%, GND1 = GND2 = 0V, T
=
40C to +85C by correlation with 100% electrical testing at T
= 25C. All other limits are assured by correlation with other
production tests and/or product design and characterization. Typical values are specified at V
CC
= +5V, T
A
= 25C.
Symbol
Parameter
Conditions
t
HDCEL
Hold Time, CE low after
From CE Low
PSCK/ASCK High
t
SUCEH
Setup Time, CE High Before
From CE Low
PSCK/ASCK Low
t
TRBH
TRB Hold Time
From CE Low
t
TRBS
TRB Setup Time
From ASCK Low and PSCK Low
t
IS
TSI, RSI Setup Time
From ASCK Low and PSCK Low
t
IH
TSI, RSI Hold Time
From ASCK Low and PSCK Low
t
PSCK/ASCK
PSCK/ASCK High and
Low Times
t
ON
TSO, RSO Turn On Time
From CE High
t
OD
TSO, RSO Propagation
From ASCK High or PSCK High
Delay Time
t
OFF
TSO, RSO Turn Off Time
From CE Low
(Valid Data to TRI-STATE)
t
CS
Setup Time for Control
From CE Low
Signals (INIT, EN,
PCM1, QSEL1, QSEL0)
t
CH
Hold Time for Control
From CE Low
Signals (INIT, EN,
PCM1, QSEL1, QSEL0)
t
RSTL
RSTB Pulse Width Low
Min
15
Typ
Max
Units
ns
15
ns
20
20
20
20
55
ns
ns
ns
ns
ns
40
40
ns
ns
20
ns
20
ns
20
ns
2
CLK
Cycles
CLK
Cycles
t
RSTH
RSTB High to the First
CE High-Low Transition
6
Note 5:
Values for 4 full-duplex (decoding and encoding) or 8 half-duplex (decoding or encoding) channels operation in a 125 μs period.
11
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