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參數(shù)資料
| 型號： | TP11362AN |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | CONNECTOR ACCESSORY |
| 中文描述： | A/MU-LAW, ADPCM CODEC, PDIP24 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-24 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大小： | 442K |
| 代理商： | TP11362AN |
Functional Description
(Continued)
by a receive (decoder) operation. For the encoding opera-
tion, the PCM data is stored in the 8-bit shift register at the
falling edge of CE while TRB is high. The TP11362A pro-
cesses the data within 123 CLK periods during the following
cycle of CE. The encoded ADPCM data is loaded into the
5-bit parallel-to-serial output register with the falling edge of
CE. The MSB data is shifted out first with the leading edge of
CE, and subsequent data is shifted out with the rising edge
of ASCK. For the decoding operation, the ADPCM data is
latched and transferred to the core at the falling edge of CE
while TRB is low. The data is processed within 123 CLK pe-
riods and the decoded 8-bit PCM data is shifted out with the
MSB first.
PSCK and ASCK are the clocks for the PCM and ADPCM
data streams, respectively. They must be high during the
transition of CE. Note that PSCK and ASCK are shown as
gated clocks as an option to conserve power. PSCK and
ASCK need only be valid while CE is high.
DS012877-5
FIGURE 3. Serial Output Structure
5
www.national.com
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TP11362AV | 制造商:Texas Instruments 功能描述: |
| TP11362AV/NOPB | 功能描述:IC PROCESSOR QUAD DIF PCM 28PLCC RoHS:是 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標準包裝:750 系列:* |
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| TP11368N | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Octal Adaptive Differential PCM Processor |
| TP11368V | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
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