參數(shù)資料
型號： TOOLSTICK300DC
廠商： Silicon Laboratories Inc
文件頁數(shù)： 51/178頁
文件大?。?/td> 0K
描述： TOOLSTICK DAUGHTER CARD
標準包裝： 1
系列： ToolStick
類型： MCU
適用于相關產(chǎn)品： C8051F300
所含物品： 子卡
C8051F300/1/2/3/4/5
144
Rev. 2.9
The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low
transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to Section
“12.1. Priority Crossbar Decoder” on page 104 for information on selecting and configuring external I/O
pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is
clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the Clock
Scale bits in CKCON (see SFR Definition 15.3).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal
/INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 8.11). Setting GATE0 to ‘1’
allows the timer to be controlled by the external input signal /INT0 (see Section “8.3.5. Interrupt Register
Descriptions” on page 75), facilitating pulse width measurements.
TR0
GATE0
/INT0
Counter/Timer
*Note: X = Don't Care
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal /INT1 is used with Timer 1; the /INT1 polarity is defined by bit IN1PL in register IT01CF (see
TCLK
TL0
(5 bits)
TH0
(8 bits)
TC
O
N
TF0
TR0
TR1
TF1
IE1
IT1
IE0
IT0
Interrupt
TR0
0
1
0
1
SYSCLK
Pre-scaled Clock
CKCON
T
2
M
H
S
C
A
0
S
C
A
1
T
2
M
L
T
1
M
T
0
M
TMOD
T
1
M
1
T
1
M
0
C
/
T
1
G
A
T
E
1
G
A
T
E
0
C
/
T
0
T
0
M
1
T
0
M
0
GATE0
/INT0
T0
Crossbar
IT01CF
I
N
1
S
L
1
I
N
1
S
L
0
I
N
1
S
L
2
I
N
1
P
L
I
N
0
P
L
I
N
0
S
L
2
I
N
0
S
L
1
I
N
0
S
L
0
IN0PL
XOR
Figure 15.1. T0 Mode 0 Block Diagram
0
X*
Disabled
10
X*
Enabled
1
0
Disabled
111
Enabled
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