
Preliminary Data Sheet
May 2001
TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
273
Agere Systems Inc.
12 28-Channel Framer Registers
(continued)
Table 378. FRM_TSLR32, Transmit Signaling Link Register 32 (R/W)
(continued)
Address
*
Bit
Name
* See
Table 376
for values of L and T.
Table 379. FRM_TSLR33, Transmit Signaling Link Register 33 (COR)
* See
Table 376
for values of L and T.
12.10 Performance Monitor Per Link Registers
The following tables describe the functions of all bits in the register map. Counters are programmable to either roll-
over or saturate, and may be programmed to clear on read.
Registers are only provisionable to clear-on-read (COR).
For each address, the register bits are identified as either read/write (R/W) or read only (RO), and the value of the
bits on reset are given.
Table 380. Performance Monitor Per Link Register Addressing Map
* L and P represent hexidecimal digits used for absolute addressing in
Table 382
through
Table 401
.
Function
Reset
Default
0
0x8LT21
2
FRM_T_FGSRC
F and G Source
. Indicates which entity will be the source for
the F and G values used in handling the ABCD bits.
0 = Host programmed.
1 = Sourced from the Rx system interface.
The F and G programming can be implied by the system
interface only when using the ASM CHI or the parallel sys-
tem interface.
FRM_T_SIGSRC[1:0]
Signaling Data Source.
Indicates which of the entities will
be the source for the ABCD bits.
00 = Signaling programmed by the host.
01 = Signaling extracted from the Rx line.
10 = Signaling received from the system interface.
1:0
00
Address
*
Bit
Name
Function
Reset
Default
0x000
0
0x8LT20
15:4
3
—
Reserved.
Must write to 0.
Time Slot 16 Multiframe Alignment Status
. A 0 indicates
that currently, time slot 16 multiframe alignment is not estab-
lished. A1 indicates that currently, time slot 16 multiframe
alignment has been established.
FRM_T_TS16AIS
Time Slot 16 AIS Detection Status
. If time slot 16 multi-
frame alignment is lost, this bit will reflect the detection of AIS
in time slot 16.
—
Reserved.
Must write to 0.
FRM_T_TS16A
2
0
1:0
00
Address Pins (ADDR15
—
ADDR0)
9
8
LNK1
LNK0
RXP = 0
TXP = 1
P*
15
0
14
0
13
12
11
10
7
1
6
0
5
4
3
2
1
0
LNK4
LNK3
LNK2
PM5
PM4 PM3 PM2 PM1
PM0
L*
—