
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
127
Agere Systems Inc.
8 TMUX Registers
(continued)
Table 143. TMUX Register Map
(continued)
Note:
The reset default of all reserved bits is 0. Shading denotes reserved bits.
Addr. Symbol Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Transmit High-speed Control Parameters
—
R/W
0x40035
TMUX_THS_
TOH_CTL
TMUX_TC
ONCAT-
MODE
TMUX_TPR
EIRDISEL
TMUX_TLR
EIRDISEL
TMUX_TSS[1:0]
TMUX_THS
LREIINH
TMUX_THS
LAISINS
TMUX_THS
APSINS
TMUX_THS
K2INS
TMUX_THS
S1INS
TMUX_THS
F1INS
TMUX_THS
Z0INS
TMUX_THS
J0INS
0x40036
TMUX_THS_
POH1_CTL
TMUX_THS
PREIINH1
TMUX_TP
OHTHRU1
TMUX_THS
N1INS1
TMUX_THS
K3INS1
TMUX_THS
F3INS1
TMUX_THS
F2INS1
TMUX_THS
RDIPINS1
TMUX_THS
C2INS1
TMUX_THS
J1INS1
0x40037
TMUX_THS_
POH2_CTL
TMUX_THS
PREIINH2
TMUX_TP
OHTHRU2
TMUX_THS
N1INS2
TMUX_THS
K3INS2
TMUX_THS
F3INS2
TMUX_THS
F2INS2
TMUX_THS
RDIPINS2
TMUX_THS
C2INS2
TMUX_THS
J1INS2
0x40038
TMUX_THS_
POH3_CTL
TMUX_THS
PREIINH3
TMUX_TP
OHTHRU3
TMUX_THS
N1INS3
TMUX_THS
K3INS3
TMUX_THS
F3INS3
TMUX_THS
F2INS3
TMUX_THS
RDIPINS3
TMUX_THS
C2INS3
TMUX_THS
J1INS3
Transmit High-speed Line RDI Control Parameters
—
R/W
0x4003A
TMUX_TLRDI
_CTL
TMUX_TRS
D_LRDIINH
TMUX_TRS
F_LRDIINH
TMUX_TRL
AISMON_L
RDIINH
TMUX_TRL
OF_LRDIIN
H
TMUX_TR
OOF_LRDII
NH
TMUX_TRL
OS_LRDIIN
H
TMUX_TRI
LOC_LRDII
NH
Transmit High-speed Path RDI Control Parameters
—
R/W
0x4003B
TMUX_TPRDI
_CTL
TMUX_TIM_PRDIINH[3:1]
TMUX_TRU
EQ_PRDIIN
H
TMUX_TRP
LM_PRDIIN
H
TMUX_TRL
OP_PRDIIN
H
TMUX_TRP
AIS_PRDII
NH
TMUX_TEP
RDI_MODE
Transmit TOH and POH Insert Values
—
R/W
0x4003C
TMUX_TZ0_I
NS_VAL
TMUX_TZ03INS[7:0]
TMUX_TZ02INS[7:0]
0x4003D
TMUX_TS1_F
1_INS_VAL
TMUX_TS1INS[7:0]
TMUX_TF1INS[7:0]
0x4003E
TMUX_TAPS
_INS_VAL
TMUX_TAPSINS[12:0]
TMUX_TK2INS[2:0]
0x4003F
TMUX_TPOH
1_INS_A
TMUX_TRDIPINS1[2:0]
TMUX_TC2INS1[7:0]
0x40040
TMUX_TPOH
1_INS_B
TMUX_TF3INS1[7:0]
TMUX_TF2INS1[7:0]
0x40041
TMUX_TPOH
1_INS_C
TMUX_TN1INS1[7:0]
TMUX_TK3INS1[7:0]
0x40042
TMUX_TPOH
2_INS_A
TMUX_TRDIPINS2[2:0]
TMUX_TC2INS2[7:0]
0x40043
TMUX_TPOH
2_INS_B
TMUX_TF3INS2[7:0]
TMUX_TF2INS2[7:0]
0x40044
TMUX_TPOH
2_INS_C
TMUX_TN1INS2[7:0]
TMUX_TK3INS2[7:0]
0x40045
TMUX_TPOH
3_INS_A
TMUX_TRDIPINS3[2:0]
TMUX_TC2INS3[7:0]
0x40046
TMUX_TPOH
3_INS_B
TMUX_TF3INS3[7:0]
TMUX_TF2INS3[7:0]
0x40047
TMUX_TPOH
3_INS_C
TMUX_TN1INS3[7:0]
TMUX_TK3INS3[7:0]