10
Agere Systems Inc.
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
Interface Specifications
3 Pin Information
Table of Contents
Contents
Page
3 Pin Information ..................................................................................................................................................10
3.1 456-Pin PBGA Pin Diagram .........................................................................................................................11
3.2 Pin Assignments...........................................................................................................................................11
3.3 Pin Descriptions ...........................................................................................................................................17
3.3.1 High-Speed I/O Pin Descriptions ...................................................................................................... 17
3.3.2 Protection Switch I/O Pin Description ............................................................................................... 18
3.3.3 Telecom Bus (Low-Speed I/O) Pin Description ................................................................................ 18
3.3.4 TOAC and POAC .............................................................................................................................. 21
3.3.5 Miscellaneous Signals ...................................................................................................................... 22
3.3.6 DS3 Port ........................................................................................................................................... 22
3.3.7 M13 Multiplexer/Demultiplexer Receive Section ............................................................................... 24
3.3.8 Low-Order Path Overhead Access Channel ..................................................................................... 25
3.3.9 Framer PLL ....................................................................................................................................... 29
3.3.10 Test Pins ......................................................................................................................................... 32
3.4 Outline Diagram ...........................................................................................................................................34
3.4.1 456-Pin PBGA .................................................................................................................................. 34
Figures
Page
Figure 2. Pin Diagram of 456-Pin PBGA (Bottom View)..........................................................................................11
Figure 3. Protection Switch......................................................................................................................................18
Figure 4. DS1/E1 to DXC Block Diagram................................................................................................................25
Tables
Page
Table 1. Pin Assignments for 456-Pin PBGA by Pin Number Order........................................................................11
Table 2. Pin Assignments for 456-Pin PBGA by Signal Name................................................................................14
Table 3. High-Speed I/O Pin Descriptions...............................................................................................................17
Table 4. Protection Switch I/O Pin Description........................................................................................................18
Table 5. Telecom Bus (Low-Speed I/O) Pin Description..........................................................................................19
Table 6. TOAC and POAC.......................................................................................................................................21
Table 7. Miscellaneous Signals ...............................................................................................................................22
Table 8. DS3 Port ....................................................................................................................................................23
Table 9. DS3 Port, C-Bit, and Datalink Access........................................................................................................24
Table 10. M13 Multiplexer/Demultiplexer Receive Section......................................................................................24
Table 11. Low-Order Path Overhead Access Channel............................................................................................25
Table 12. Multifunction System Interface Transmit Path Direction ..........................................................................26
Table 13. Framer PLL..............................................................................................................................................29
Table 14. Microprocessor Interfaces........................................................................................................................30
Table 15. General-Purpose Interface.......................................................................................................................31
Table 16. Test Pins ..................................................................................................................................................32
Table 17. CDR Power..............................................................................................................................................32
Table 18. LVDS Control Pins ...................................................................................................................................32