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參數(shù)資料
| 型號(hào)： | TMX32C6411ZLZ |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | FIXED POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 92/119頁(yè) |
| 文件大?。?/td> | 1742K |
| 代理商： | TMX32C6411ZLZ |
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SPRS196H MARCH 2002 REVISED JULY 2004
92
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
RESET TIMING (CONTINUED)
ECLKOUT2
17
14
1
CLKOUT4
CLKOUT6
RESET
ECLKIN
Low Group
Z Group§
Boot and Device
Configuration Inputs§
16
15
3
2
10
8
EMIF Z Group§
EMIF High Group
EMIF Low Group
11
9
7
6
13
12
ECLKOUT1
5
4
PCLK
18
EMIF Z group consists of:
EA[22:3], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE,
SOE3, SDCKE, and PDT.
EMIF high group consists of: HOLDA (when the corresponding HOLD input is high)
EMIF low group consists of:
BUSREQ; HOLDA (when the corresponding HOLD input is low)
Low group consists of:
XSP_CS, XSP_CLK, and XSP_DO; all of which apply only when PCI EEPROM (EEAI) is enabled
(with PCI_EN = 1). Otherwise, the XSP_CLK and XSP_DO pins are in the Z group. For more details
on the PCI configuration pins, see the Device Configurations section of this data sheet.
Z group consists of:
HD[31:0]/AD[31:0], CLKX0, CLKX1, XSP_CLK, FSX0, FSX1, DX0, DX1, XSP_DO, CLKR0, CLKR1,
FSR0, FSR1, TOUT0, TOUT1, GP[8:0], GP10/PCBE3, HR/W/PCBE2, HDS2/PCBE1, PCBE0,
GP13/PINTA, GP11/PREQ, HDS1/PSERR, HCS/PPERR, HCNTL1/PDEVSEL, HAS/PPAR,
HCNTL0/PSTOP, HHWIL/PTRDY (16-bit HPI mode only), HRDY/PIRDY, and HINT/PFRAME.
If LEND, BOOTMODE[1:0], ECLKIN_SEL[1:0], EEAI, and HD5/AD5 pins are actively driven, care must be taken to ensure no timing contention
between parameters 6, 7, 14, 15, 16, and 17.
§Boot and Device Configurations Inputs (during reset) include: LEND, BOOTMODE[1:0], ECLKIN_SEL[1:0], EEAI, and HD5/AD5.
The PCI_EN pin
must
be driven valid at all times and the user
must not
switch values throughout device operation.
Figure 37. Reset Timing
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