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參數(shù)資料
| 型號(hào)： | TMX32C6411ZLZ |
| 廠商： | Texas Instruments, Inc. |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | FIXED POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 59/119頁(yè) |
| 文件大小： | 1742K |
| 代理商： | TMX32C6411ZLZ |
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SPRS196H MARCH 2002 REVISED JULY 2004
59
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
clock PLL (continued)
PLLMULT
1
0
PLLCLK
CLKMODE0
(See Table 24)
CLKIN
C2
C1
EMI
filter
3.3 V
/2
/8
/4
/6
00 01 10
CPU Clock
Configuration Bus
Timer Internal Clock
CLKOUT4,
McBSP Internal Clock
CLKOUT6
ECLKIN_SEL[1:0]
/2
/4
EMIF
00 01 10
EK2RATE
(GBLCTL.[19,18])
ECLKOUT2
ECLKOUT1
PLL x6
10
μ
F
0.1
μ
F
ECLKIN
(For the PLL Options, CLKMODE0 Pin Setup, and
PLL Clock Frequency Ranges, see Table 24.)
Internal to C6411
PLLV
NOTES: A. Place all PLL external components (C1, C2, and the EMI Filter) as close to the C6000
DSP device as possible. For the best
performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or
components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI
Filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U.
Figure 6. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode
Table 24. TMS320C6411 PLL Multiply Factor Options, Clock Frequency Ranges, and Typical Lock Time
GLZ and ZLZ PACKAGE 23 x 23 mm BGA
CLKMODE0
CLKMODE
(PLL MULTIPLY
FACTORS)
CLKIN
RANGE
(MHz)
CPU CLOCK
FREQUENCY
RANGE (MHz)
CLKOUT4
RANGE (MHz)
CLKOUT6
RANGE (MHz)
TYPICAL
LOCK TIME
(
μ
s)§
N/A
0
Bypass (x1) [default]
3075.75
3075.75
7.518.93
512.62
1
x6
3050.5
180303
4575.75
3050.5
75
These clock frequency range values are applicable to a C6411300 speed device.
Use an external pullup resistor on the CLKMODE0 pin to set the C6411 device to the valid PLL multiply clock mode (x6). With an internal pulldown
resistor on the CLKMODE0 pin, the default clock mode is x1 (bypass).
§Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if
the typical lock time is specified as 100
μ
s, the maximum value may be as long as 250
μ
s.
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