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SPRS196H MARCH 2002 REVISED JULY 2004
75
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
ASYNCHRONOUS MEMORY TIMING
timing requirements for asynchronous memory cycles
(see Figure 22 and Figure 23)
NO.
300
UNIT
MIN
MAX
3
tsu(EDV-AREH)
th(AREH-EDV)
tsu(ARDY-EKO1H)
Setup time, EDx valid before ARE high
6.5
ns
4
Hold time, EDx valid after ARE high
1
ns
6
Setup time, ARDY valid before ECLKOUTx high
3
1
ns
ns
7
th(EKO1H-ARDY)
Hold time, ARDY valid after ECLKOUTx high
Rev 1.1
Rev 2.0
1.3
ns
To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is
only
recognized
two cycles before the end of the programmed strobe time and while ARDY is low, the strobe time is extended cycle-by-cycle. When ARDY is
recognized low, the end of the strobe time is two cycles after ARDY is recognized high. To use ARDY as an asynchronous input, the pulse width
of the ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met.
RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
switching characteristics over recommended operating conditions for asynchronous memory
cycles
§
(see Figure 22 and Figure 23)
NO.
PARAMETER
300
MIN
UNIT
MAX
1
tosu(SELV-AREL)
toh(AREH-SELIV)
td(EKO1H-AREV)
tosu(SELV-AWEL)
toh(AWEH-SELIV)
td(EKO1H-AWEV)
Output setup time, select signals valid to ARE low
RS * E 1.5
ns
2
Output hold time, ARE high to select signals invalid
RS * E 1.9
ns
5
Delay time, ECLKOUTx high to ARE vaild
1
7
ns
8
Output setup time, select signals valid to AWE low
WS * E 1.7
ns
9
Output hold time, AWE high to select signals invalid
WH * E 1.8
ns
10
Delay time, ECLKOUTx high to AWE vaild
1.3
7.1
ns
RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
§E = ECLKOUT1 period in ns
Select signals for EMIF include: CEx, BE[3:0], EA[22:3], AOE; and for EMIF writes, include ED[31:0].