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| 型號： | TMX32C6411GLZ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Anti-Static Storage Bags; External Height:5"; External Width:3"; Thickness:0.12" |
| 中文描述： | 定點數(shù)字信號處理器 |
| 文件頁數(shù)： | 7/119頁 |
| 文件大?。?/td> | 1742K |
| 代理商： | TMX32C6411GLZ |
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SPRS196H MARCH 2002 REVISED JULY 2004
7
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
description
The TMS320C64x
DSPs (including the TMS320C6411 device) are the highest-performance fixed-point DSP
generation in the TMS320C6000
DSP platform. The TMS320C6411 (C6411) device is based on the
second-generation high-performance, advanced VelociTI
very-long-instruction-word (VLIW) architecture
(VelocTI.2
) developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel
and multifunction applications. The C64x
is a code-compatible member of the C6000
DSP platform.
With performance of up to 2400 million instructions per second (MIPS) at a clock rate of 300 MHz, the C6411
device offers cost-effective solutions to high-performance DSP programming challenges. The C6411 DSP
possesses the operational flexibility of high-speed controllers and the numerical capability of array processors.
The C64x
DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly
independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)— with
VelociTI.2
extensions. The VelociTI.2
extensions in the eight functional units include new instructions to
accelerate the performance in key applications and extend the parallelism of the VelociTI
architecture. The
C6411 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 600 million MACs per second
(MMACS), or eight 8-bit MACs per cycle for a total of 2400 MMACS. The C6411 DSP also has
application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other
C6000
DSP platform devices.
The C6411 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The
Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit
2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 2-Mbit memory space that is shared
between program and data space. L2 memory can be configured as mapped memory or combinations of cache
(up to 256K bytes) and mapped memory. The peripheral set includes two multichannel buffered serial ports
(McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface
(HPI16/HPI32); a peripheral component interconnect (PCI); a general-purpose input/output port (GPIO) with
16 GPIO pins; and a glueless external memory interface (32-bit EMIF), which is capable of interfacing to
synchronous and asynchronous memories and peripherals.
The C6411 has a complete set of development tools which includes: a new C compiler, an assembly optimizer
to simplify programming and scheduling, and a Windows
debugger interface for visibility into source code
execution.
TMS320C6000, C64x, and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
Other trademarks are the property of their respective owners.
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