參數(shù)資料
型號(hào): TMX320F28069UPFPA
廠商: Texas Instruments
文件頁數(shù): 85/174頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 128KB FLASH 80HTQFP
產(chǎn)品培訓(xùn)模塊: ControlSUITE
Piccolo F2806x
標(biāo)準(zhǔn)包裝: 1
系列: TMS320F2806x, Piccolo™, C2000™
核心處理器: C28x
芯體尺寸: 32-位
速度: 80MHz
連通性: CAN,I²C,McBSP,SCI,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 40
程序存儲(chǔ)器容量: 256KB(128K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 50K x 16
電壓 - 電源 (Vcc/Vdd): 1.71 V ~ 1.995 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 80-TQFP 裸露焊盤
包裝: 托盤
其它名稱: 296-30085
TMX320F28069UPFPA-ND
SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012
Peripheral Frame 1 and Peripheral Frame 2 are grouped together to enable these blocks to be write/read
peripheral block protected. The protected mode makes sure that all accesses to these blocks happen as
written. Because of the pipeline, a write immediately followed by a read to different memory locations, will
appear in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral
applications where the user expected the write to occur first (as written). The CPU supports a block
protection mode where a region of memory can be protected so that operations occur as written (the
penalty is extra cycles are added to align the operations). This mode is programmable and by default, it
protects the selected zones.
The wait-states for the various spaces in the memory map area are listed in Table 2-4.
Table 2-4. Wait-States
AREA
WAIT-STATES (CPU)
COMMENTS
M0 and M1 SARAMs
0-wait
Fixed
Peripheral Frame 0
0-wait
Peripheral Frame 1
0-wait (writes)
Cycles can be extended by peripheral-generated ready.
2-wait (reads)
Back-to-back write operations to Peripheral Frame 1 registers will incur
a 1-cycle stall (1-cycle delay).
Peripheral Frame 2
0-wait (writes)
Fixed. Cycles cannot be extended by the peripheral.
2-wait (reads)
Peripheral Frame 3
0-wait (writes)
Assumes no conflict between CPU and CLA/DMA cycles. The wait
states can be extended by peripheral-generated ready.
2-wait (reads)
L0–L8 SARAM
0-wait data and program
Assumes no CPU conflicts
OTP
Programmable
Programmed via the Flash registers.
1-wait minimum
1-wait is minimum number of wait states allowed.
FLASH
Programmable
Programmed via the Flash registers.
0-wait Paged min
1-wait Random min
Random
≥ Paged
FLASH Password
16-wait fixed
Wait states of password locations are fixed.
Boot-ROM
0-wait
18
Device Overview
Copyright 2010–2012, Texas Instruments Incorporated
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