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參數(shù)資料
型號: TMX320F28069UPFPA
廠商: Texas Instruments
文件頁數(shù): 58/174頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 128KB FLASH 80HTQFP
產(chǎn)品培訓(xùn)模塊: ControlSUITE
Piccolo F2806x
標準包裝: 1
系列: TMS320F2806x, Piccolo™, C2000™
核心處理器: C28x
芯體尺寸: 32-位
速度: 80MHz
連通性: CAN,I²C,McBSP,SCI,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 40
程序存儲器容量: 256KB(128K x 16)
程序存儲器類型: 閃存
RAM 容量: 50K x 16
電壓 - 電源 (Vcc/Vdd): 1.71 V ~ 1.995 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 80-TQFP 裸露焊盤
包裝: 托盤
其它名稱: 296-30085
TMX320F28069UPFPA-ND
WAKE INT
(A)(B)
XCLKOUT
Address/Data
(internal)
td(WAKEIDLE)
tw(WAKEINT)
SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012
5.23.1.4 Low-Power Mode Wakeup Timing
Table 5-70 shows the timing requirements, Table 5-71 shows the switching characteristics, and Figure 5-
54 shows the timing diagram for IDLE mode.
Table 5-70. IDLE Mode Timing Requirements(1)
MIN
MAX
UNIT
Without input qualifier
2tc(SCO)
tw(WAKE-INT)
Pulse duration, external wake-up signal
cycles
With input qualifier
5tc(SCO) + tw(IQSW)
(1)
For an explanation of the input qualifier parameters, see Table 5-69.
Table 5-71. IDLE Mode Switching Characteristics(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Delay time, external wake signal to program execution resume (2)
cycles
Without input qualifier
20tc(SCO)
cycles
Wake-up from Flash
Flash module in active state
With input qualifier
20tc(SCO) + tw(IQSW)
td(WAKE-IDLE)
Without input qualifier
1050tc(SCO)
cycles
Wake-up from Flash
Flash module in sleep state
With input qualifier
1050tc(SCO) + tw(IQSW)
Without input qualifier
20tc(SCO)
cycles
Wake-up from SARAM
With input qualifier
20tc(SCO) + tw(IQSW)
(1)
For an explanation of the input qualifier parameters, see Table 5-69.
(2)
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake-up) signal involves additional latency.
A.
WAKE INT can be any enabled interrupt, WDINT or XRS. After the IDLE instruction is executed, a delay of 5
OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.
B.
From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be
initiated until at least 4 OSCCLK cycles have elapsed.
Figure 5-54. IDLE Entry and Exit Timing
150
Peripheral and Electrical Specifications
Copyright 2010–2012, Texas Instruments Incorporated
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