參數(shù)資料
型號(hào)： TMX320C6415TGLZ
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： FIXED-POINT DIGITAL SIGNAL PROCESSORS
中文描述： 定點(diǎn)數(shù)字信號(hào)處理器
文件頁數(shù)： 51/140頁
文件大?。?/td> 2033K
代理商： TMX320C6415TGLZ
SPRS226H NOVEMBER 2003 REVISED AUGUST 2005
51
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Terminal Functions (Continued)
SIGNAL
TYPE
IPD/
IPU
DESCRIPTION
NAME
NO.
EMIFB (16-bit) DATA
||
BED15
D7
BED14
B6
BED13
C7
BED12
A6
BED11
D8
BED10
B7
BED9
C8
BED8
A7
I/O/Z
IPU
EMIFB external data
BED7
C9
BED6
B8
BED5
D9
BED4
B9
BED3
C10
BED2
A9
BED1
D10
BED0
B10
MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP2)
MCBSP2_EN
AF3
I
IPD
McBSP2 enable pin. This pin works in conjunction with the PCI_EN pin to enable/disable other
peripherals (for more details, see the Device Configurations section of this data sheet).
CLKS2/GP8§
AE4
I/O/Z
IPD
McBSP2 external clock source (CLKS2) [
input only
] [default] or this pin can also be
programmed as a GPIO 8 pin (
I/O/Z
).
CLKR2
AB1
I/O/Z
IPD
McBSP2 receive clock. When McBSP2 is disabled (PCI_EN pin = 1 and MCBSP2_EN
pin = 0), this pin is tied-off.
CLKX2/
XSP_CLK§
AC2
I/O/Z
IPD
McBSP2 transmit clock (
I/O/Z
) [default] or PCI serial interface clock (
O
).
DR2/XSP_DI§
AB3
I
IPU
McBSP2 receive data (
I
) [default] or PCI serial interface data in (
I
). In PCI mode, this pin is
connected to the output data pin of the serial PROM.
DX2/XSP_DO§
AA2
O/Z
IPU
McBSP2 transmit data (
O/Z
) [default] or PCI serial interface data out (
O
). In PCI mode, this pin
is connected to the input data pin of the serial PROM.
FSR2
AC1
I/O/Z
IPD
McBSP2 receive frame sync. When McBSP2 is disabled (PCI_EN pin = 1 and MCBSP2_EN
pin = 0), this pin is tied-off.
FSX2
AB2
I/O/Z
IPD
McBSP2 transmit frame sync. When McBSP2 is disabled (PCI_EN pin = 1 and MCBSP2_EN
pin = 0), this pin is tied-off.
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k
IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
§For the C6415T and C6416T devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
The C6414T device does
not
support the PCI or UTOPIA peripherals; therefore, these muxed peripheral pins except CLKS2/GP8 are standalone
peripheral functions for this device.
||These C64x
devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal
whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of
discussion, the prefix “A” or “B” may be omitted from the signal name.
To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
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