參數(shù)資料
型號: TMX320C6415TGLZ
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: FIXED-POINT DIGITAL SIGNAL PROCESSORS
中文描述: 定點(diǎn)數(shù)字信號處理器
文件頁數(shù): 35/140頁
文件大?。?/td> 2033K
代理商: TMX320C6415TGLZ
SPRS226H NOVEMBER 2003 REVISED AUGUST 2005
35
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
signal groups description (continued)
McBSPs
(Multichannel Buffered
Serial Ports)
CLKX0
FSX0
DX0
CLKR0
FSR0
DR0
CLKS0
Transmit
McBSP0
Receive
Clock
CLKX1/URADDR4
FSX1/UXADDR3
DX1/UXADDR4
CLKR1/URADDR2
FSR1/UXADDR2
DR1/UXADDR1
CLKS1/URADDR3
Transmit
McBSP1
Receive
Clock
CLKX2/XSP_CLK
FSX2
DX2/XSP_DO
CLKR2
FSR2
DR2/XSP_DI
CLKS2/GP8
Transmit
McBSP2
Receive
Clock
For the C6415T and C6416T devices, these McBSP2 and McBSP1 pins are muxed with the PCI and UTOPIA peripherals, respectively.
By default, these signals function as McBSP2 and McBSP1, respectively. For more details on these muxed pins, see the Device
Configurations section of this data sheet.
For the C6414T device, these McBSP2 and McBSP1 peripheral pins are
not
muxed; the C6414T device does
not
support PCI and
UTOPIA peripherals.
The McBSP2 clock source pin (CLKS2, default) is muxed with the GP8 pin. To use this muxed pin as the GP8 signal, the appropriate
GPIO register bits (GP8EN and GP8DIR) must be properly enabled and configured. For more details, see the Device Configurations
section of this data sheet.
Figure 4. Peripheral Signals (Continued)
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