參數(shù)資料
型號: TMS470R1A256PZ
廠商: Texas Instruments, Inc.
英文描述: 16/32-Bit RISC Flash Microcontroller
中文描述: 16/32位RISC閃存微控制器
文件頁數(shù): 3/46頁
文件大小: 392K
代理商: TMS470R1A256PZ
www.ti.com
TMS470R1A256
16/32-Bit RISC Flash Microcontroller
SPNS100–NOVEMBER 2004
The functions performed by the 470+ system module (SYS) include:
Address decoding
Memory protection
Memory and peripherals bus supervision
Reset and abort exception management
Prioritization for all internal interrupt sources
Device clock control
Parallel signature analysis (PSA)
This data sheet includes device-specific information such as memory and peripheral select assignment,
interrupt priority, and a device memory map. For a more detailed functional description of the SYS module,
see the
TMS470R1x System Module Reference Guide
(literature number SPNU189).
256K-byte Flash
12K-byte SRAM
Zero-pin phase-locked loop (ZPLL) clock module
Analog watchdog (AWD) timer
Real-time interrupt ( RTI) module
Two serial peripheral interface (SPI) modules
Two serial communications interface (SCI) modules
Standard CAN controller (SCC)
Class II serial interface (C2SIb)
10-bit multi-buffered analog-to-digital converter (MibADC), 16-input channels
High-end timer (HET) controlling 16 I/Os
External Clock Prescale (ECP)
Up to 49 I/O pins and 1 input-only pin
The A256 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte,
half-word, and word modes.
The Flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented
with a 32-bit-wide data bus interface.The Flash operates with a system clock frequency of up to 24 MHz. In
pipeline mode, the Flash operates with a system clock frequency of up to 48 MHz. For more detailed information
on the Flash, see the
Flash
section of this data sheet and the
TMS470R1x F05 Flash Reference Guide
(literature
number SPNU213).
The A256 device has six communication interfaces: two SPIs, two SCIs, an SCC, and a C2SIb. The SPI provides
a convenient method of serial interaction for high-speed communications between similar shift-register type
devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication between the
CPU and other peripherals using the standard Non-Return-to-Zero (NRZ) format. The SCC uses a serial,
multimaster communication protocol that efficiently supports distributed real-time control with robust communi-
cation rates of up to 1 megabit per second (Mbps). The SCC is ideal for applications operating in noisy and
harsh environments (e.g., industrial fields) that require reliable serial communication or multiplexed wiring. The
C2SIb allows the A256 to transmit and receive messages on a class II network following an SAE J1850
(2)
standard. For more detailed functional information on the SPI, SCI, and SCC peripherals, see the specific
reference guides (literature numbers SPNU195, SPNU196, and SPNU197, respectively). For more detailed
functional information on the C2SIb peripheral, see the
TMS470R1x Class II Serial Interface B (C2SIb)
Reference Guide
(literature number SPNU214).
The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications.
The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an
attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well suited
for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses.
For more detailed functional information on the HET, see the
TMS470R1x High-End Timer (HET) Reference
Guide
(literature number SPNU199).
(2)
SAE Standard J1850 Class B Data Communication Network Interface
3
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