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| 型號： | TMS417409ADJ-60 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES |
| 中文描述： | 4194304 4位擴展數(shù)據(jù)輸出動態(tài)隨機存取存儲器 |
| 文件頁數(shù)： | 16/37頁 |
| 文件大小： | 515K |
| 代理商： | TMS417409ADJ-60 |
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TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
16
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 4) (continued)
’41x409A-50
’42x409A-50
’41x409A-60
’42x409A-60
’41x409A-70
’42x409A-70
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
tAWD
Delay time, column address to write command
(read-write only)
42
49
57
ns
tCPW
tCRP
tCWD
tOED
tRAD
tRAL
tCAL
tRCD
tRPC
tRSH
tRWD
tTAA
tTCPA
tTRAC
tT
Delay time, W low after xCAS precharge (read-write only)
45
54
62
ns
Delay time, CAS precharge to RAS
5
5
5
ns
Delay time, CAS to write command (read-write only)
30
34
40
ns
Delay time, OE to data in
13
15
18
ns
Delay time, RAS to column address (see Note 11)
10
25
12
30
12
35
ns
Delay time, column address to RAS precharge
25
30
35
ns
Delay time, column address to CAS precharge
18
20
25
ns
Delay time, RAS to CAS (see Note 11)
12
37
14
45
14
52
ns
Delay time, RAS precharge to CAS
5
5
5
ns
Delay time, CAS active to RAS precharge
8
10
12
ns
Delay time, RAS to write command (read-write only)
67
79
92
ns
Access time from address (test mode)
30
35
40
ns
Access time, from column precharge (test mode)
35
40
45
ns
Access time, from RAS (test mode)
55
65
75
ns
Transition time
2
30
2
30
2
30
ns
tREF
Refresh time interval
’4x6409A
64
64
64
ms
’4x7409A
32
32
32
ms
NOTES:
4. With ac parameters, it is assumed that tT = 2 ns.
11. The maximum value is specified only to ensure access time.
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| TMS417409A | 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES |
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| TMS427409A | 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS427409ADGA-60 | 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES |
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