參數(shù)資料
型號： TMS320F2812PGFMEP
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 96/159頁
文件大?。?/td> 2084K
代理商： TMS320F2812PGFMEP
Electrical Specifications
96
March 2004 Revised October 2004
SGUS051A
6.9
Signal Transition Levels
Note that some of the signals use different reference voltages, see the recommended operating conditions
table. Output levels are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of
0.4 V.
Figure 65 shows output levels.
0.4 V (VOL)
20%
2.4 V (VOH)
80%
Figure 65. Output Levels
Output transition times are specified as follows:
For a
high-to-low
transition
, the level at which the output is said to be no longer high is below 80% of the
total voltage range and lower and the level at which the output is said to be low is 20% of the total voltage
range and lower.
For a
low-to-high transition
, the level at which the output is said to be no longer low is 20% of the total
voltage range and higher and the level at which the output is said to be high is 80% of the total voltage
range and higher.
Figure 66 shows the input levels.
0.8 V (VIL)
10%
2.0 V (VIH)
90%
Figure 66. Input Levels
Input transition times are specified as follows:
For a
high-to-low transition
on an input signal, the level at which the input is said to be no longer high is
90% of the total voltage range and lower and the level at which the input is said to be low is 10% of the
total voltage range and lower.
For a
low-to-high transition
on an input signal, the level at which the input is said to be no longer low is
10% of the total voltage range and higher and the level at which the input is said to be high is 90% of the
total voltage range and higher.
NOTE:
See the individual timing diagrams for levels used for testing timing parameters.
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