參數(shù)資料
型號： TMS320F2812PGFMEP
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 126/159頁
文件大小： 2084K
代理商： TMS320F2812PGFMEP
Electrical Specifications
125
March 2004 Revised October 2004
SGUS051A
6.25
External Interface Write Timing
Table 629. External Memory Interface Write Switching Characteristics
PARAMETER
MIN
MAX
UNIT
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
td(XCOHL-XWEL)
td(XCOHL-XWEH)
td(XCOH-XRNWL)
td(XCOHL-XRNWH)
ten(XD)XWEL
td(XWEL-XD)
th(XA)XZCSH
th(XD)XWE
tdis(XD)XRNW
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
TW = Trail period, write access. See Table 625.
Delay time, XCLKOUT high to zone chip-select active low
1
ns
Delay time, XCLKOUT high or low to zone chip-select inactive high
2
3
ns
Delay time, XCLKOUT high to address valid
2
ns
Delay time, XCLKOUT high/low to XWE low
2
ns
Delay time, XCLKOUT high/low to XWE high
2
ns
Delay time, XCLKOUT high to XR/W low
1
ns
Delay time, XCLKOUT high/low to XR/W high
2
1
ns
Enable time, data bus driven from XWE low
0
ns
Delay time, data valid after XWE active low
4
ns
Hold time, address valid after zone chip-select inactive high
ns
Hold time, write data valid after XWE inactive high
TW2
ns
Data bus disabled after XR/W inactive high
4
ns
Lead
Active
Trail
td(XCOH-XZCSL)
td(XCOH-XA)
td(XCOHL-XWEL)
td(XCOHL-XWEH)
td(XCOHL-XZCSH)
ten(XD)XWEL
th(XD)XWEH
tdis(XD)XRNW
XCLKOUT=XTIMCLK
XCLKOUT=1/2 XTIMCLK
XZCS0AND1, XZCS2,
XZCS6AND7
XA[0:18]
XRD
XWE
XR/W
XD[0:15]
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment
cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. For USEREADY = 0, the external XREADY input signal is ignored.
D. XA[0:18] will hold the last address put on the bus during inactive cycles, including alignment cycles.
td(XCOH-XRNWL)
td(XCOHL-XRNWH)
DOUT
XREADY
td(XWEL-XD)
Figure 630. Example Write Access
XTIMING register parameters used for this example:
XRDLEAD
N/A
N/A = “Don’t care” for this example
XRDACTIVE
N/A
XRDTRAIL
N/A
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
N/A
0
0
≥
1
≥
0
≥
0
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