參數(shù)資料
型號(hào): TMS320F2812PGFMEP
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: Digital Signal Processors
中文描述: 數(shù)字信號(hào)處理器
文件頁數(shù): 95/159頁
文件大?。?/td> 2084K
代理商: TMS320F2812PGFMEP
Electrical Specifications
95
March 2004 Revised October 2004
SGUS051A
VDD_3.3V
2.5 V
(see Note A)
3.3 V
VDD_1.8V
XRS
1.8 V (or
1.9 V)
XRS
> 8
μ
s
1.5 V
3.3 V
<10 ms
>1 ms
Power-Up Sequence
Power-Down Sequence
1.8 V (or
1.9 V)
VDD_3.3V
VDD_1.8V
VDDIO, VDD3VFL, VDDAIO, VDDA1, VDDA2, AVDDREFBG
VDD, VDD1
NOTES: A. 1.8-V (or 1.9 V) supply should ramp after the 3.3-V supply reaches at least 2.5 V.
B. Reset (XRS) should remain low until supplies and clocks are stable. See Figure 69, Power-on Reset in Microcomputer Mode
(XMP/MC = 0), for minimum requirements.
C. Voltage supervisor or LDO reset control will trip reset (XRS) first when the 3.3-V supply is off regulation. Typically, this occurs
a few milliseconds before the 1.8-V (or 1.9 V) supply reaches 1.5 V.
D. Keeping reset low (XRS) at least 8
μ
s prior to the 1.8-V (or 1.9 V) supply reaching 1.5 V will keep the flash module in complete
reset before the supplies ramp down.
E. Since the state of GPIO pins is undefined until the 1.8-V (or 1.9 V) supply reaches at least 1 V, this supply should be ramped
as quickly as possible (after the 3.3-V supply reaches at least 2.5 V).
F. Other than the power supply pins, no pin should be driven before the 3.3-V rail has been fully powered up.
See Note B
See Note D
See Note C
Figure 64. F2812/F2811/F2810 Typical Power-Up and Power-Down Sequence Option 2
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