參數(shù)資料
型號： TMS320F2812PGFMEP
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 43/159頁
文件大?。?/td> 2084K
代理商： TMS320F2812PGFMEP
Functional Overview
43
March 2004 Revised October 2004
SGUS051A
The operation and timing of the external interface, can be controlled by the registers listed in Table 38.
Table 38. XINTF Configuration and Control Register Mappings
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
XTIMING0
0x00 0B20
2
XINTF Timing Register, Zone 0 can access as two 16-bit registers or one 32-bit register
XTIMING1
0x00 0B22
2
XINTF Timing Register, Zone 1 can access as two 16-bit registers or one 32-bit register
XTIMING2
0x00 0B24
2
XINTF Timing Register, Zone 2 can access as two 16-bit registers or one 32-bit register
XTIMING6
0x00 0B2C
2
XINTF Timing Register, Zone 6 can access as two 16-bit registers or one 32-bit register
XTIMING7
0x00 0B2E
2
XINTF Timing Register, Zone 7 can access as two 16-bit registers or one 32-bit register
XINTCNF2
0x00 0B34
2
XINTF Configuration Register can access as two 16-bit registers or one 32-bit register
XBANK
0x00 0B38
1
XINTF Bank Control Register
XREVISION
0x00 0B3A
1
XINTF Revision Register
3.5.1
Timing Registers
XINTF signal timing can be tuned to match specific external device requirements such as setup and hold times
to strobe signals for contention avoidance and maximizing bus efficiency. The timing parameters can be
configured individually for each zone. This allows the programmer to maximize the efficiency of the bus, based
on the type of memory or peripheral that the user needs to access. All XINTF timing values are with respect
to XTIMCLK, which is equal to or one-half of the SYSCLKOUT rate, as shown in Figure 628.
For detailed information on the XINTF timing and configuration register bit fields, see the
TMS320F28x DSP
External Interface (XINTF) Reference Guide
(literature number SPRU067).
3.5.2
XREVISION Register
The XREVISION register contains a unique number to identify the particular version of XINTF used in the
product. For the 2812, this register will be configured as described in Table 39.
Table 39. XREVISION Register Bit Definitions
BIT(S)
NAME
TYPE
RESET
DESCRIPTION
150
REVISION
R
0x0004
Current XINTF Revision. For internal use/reference. Test purposes only. Subject to
change.
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