參數(shù)資料
型號： TMS320F243PGES
元件分類： 數(shù)字信號處理
英文描述： 16-Bit Digital Signal Processor
中文描述： 16位數(shù)字信號處理器
文件頁數(shù)： 58/116頁
文件大?。?/td> 1485K
代理商： TMS320F243PGES
TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999
58
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
CAN memory map (continued)
Table 18. Mailbox Addresses
ADDRESS
OFFSET [5:0]
NAME
DESCRIPTION
UPPER HALF-WORD ADDRESS BIT 0 = 1
DESCRIPTION
LOWER HALF-WORD ADDRESS BIT 0 = 0
00h
MSGID0
Message ID for mailbox 0
Message ID for mailbox 0
02h
MSGCTRL0
Unused
RTR and DLC (bits 4 to 0)
04h
Datalow0
Databyte 0, Databyte 1 (DBO = 1)
Databyte 2, Databyte 3 (DBO = 1)
Databyte 3, Databyte 2 (DBO = 0)
Databyte 1, Databyte 0 (DBO = 0)
06h
Datahigh0
Databyte 4, Databyte 5 (DBO = 1)
Databyte 6, Databyte 7 (DBO = 1)
Databyte 7, Databyte 6 (DBO = 0)
Databyte 5, Databyte 4 (DBO = 0)
08h
MSGID1
Message ID for mailbox 1
Message ID for mailbox 1
0Ah
MSGCTRL1
Unused
RTR and DLC (bits 4 to 0)
0Ch
Datalow1
Databyte 0, Databyte 1 (DBO = 1)
Databyte 2, Databyte 3 (DBO = 1)
Databyte 3, Databyte 2 (DBO = 0)
Databyte 1, Databyte 0 (DBO = 0)
0Eh
Datahigh1
Databyte 4, Databyte 5 (DBO = 1)
Databyte 6, Databyte 7 (DBO = 1)
...
...
...
...
28h
MSGID5
Message ID for mailbox 5
Message ID for mailbox 5
2Ah
MSGCTRL5
Unused
RTR and DLC (bits 4 to 0)
2Ch
Datalow5
Databyte 0, Databyte 1 (DBO = 1)
Databyte 2, Databyte 3 (DBO = 1)
Databyte 3, Databyte 2 (DBO = 0)
Databyte 3, Databyte 2 (DBO = 0)
2Eh
Datahigh5
Databyte 4, Databyte 5 (DBO = 1)
Databyte 7, Databyte 6 (DBO = 0)
Databyte 6, Databyte 7 (DBO = 1)
Databyte 5, Databyte 4 (DBO = 0)
The DBO (Data Byte Order) bit is located in the MCR register and is used to define the order in which the data bytes are stored in the mailbox
when received and the order in which the data bytes are transmitted. Byte 0 is the first byte in the message and Byte 7 is the last one as shown
in the CAN message.
CAN interrupt logic
There are two interrupt requests from the CAN module to the Peripheral Interrupt Expansion (PIE) controller:
the Mailbox Interrupt and the Error Interrupt. Both interrupts can assert either a high-priority request or a
low-priority request to the CPU. The following events can initiate an interrupt:
Transmission Interrupt
A message was transmitted or received successfully—asserts the Mailbox Interrupt.
Abort Acknowledge Interrupt
A send transmission was aborted—asserts the Error Interrupt.
Write Denied Interrupt
The CPU tried to write to a mailbox but was not allowed to—asserts the Error Interrupt.
Wakeup Interrupt
After wakeup, this interrupt is generated—asserts the Error Interrupt, even when clocks are not running.
Receive Message Lost Interrupt
An old message was overwritten by a new one—asserts the Error Interrupt.
Bus-Off Interrupt
The CAN module enters the bus-off state—asserts the Error Interrupt.
Error Passive Interrupt
The CAN module enters the error passive mode—asserts the Error Interrupt.
Warning Level Interrupt
One or both of the error counters is greater than or equal to 96—asserts the Error Interrupt.
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