參數(shù)資料
型號： TMS320F243PGES
元件分類： 數(shù)字信號處理
英文描述： 16-Bit Digital Signal Processor
中文描述： 16位數(shù)字信號處理器
文件頁數(shù)： 57/116頁
文件大?。?/td> 1485K
代理商： TMS320F243PGES
TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999
57
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
CAN memory map (continued)
Table 17. Register Addresses
ADDRESS
OFFSET
NAME
DESCRIPTION
00h
MDER
Mailbox Direction/Enable Register (bits 7 to 0)
01h
TCR
Transmission Control Register (bits 15 to 0)
02h
RCR
Receive Control Register (bits 15 to 0)
03h
MCR
Master Control Register (bits 13 to 6, 1, 0)
04h
BCR2
Bit Configuration Register 2 (bits 7 to 0)
05h
BCR1
Bit Configuration Register 1 (bits 10 to 0)
06h
ESR
Error Status Register (bits 8 to 0)
07h
GSR
Global Status Register (bits 5 to 0)
08h
CEC
Transmit and Receive Error Counters (bits 15 to 0)
09h
CAN_IFR
Interrupt Flag Register (bits 13 to 8, 6 to 0)
0Ah
CAN_IMR
Interrupt Mask Register (bits 15, 13 to 0)
0Bh
LAM0_H
Local Acceptance Mask Mailbox 0 and 1 (bits 31, 28 to 16)
0Ch
LAM0_L
Local Acceptance Mask Mailbox 0 and 1 (bits 15 to 0)
0Dh
LAM1_H
Local Acceptance Mask Mailbox 2 and 3 (bits 31, 28 to 16)
0Eh
LAM1_L
Local Acceptance Mask Mailbox 2 and 3 (bits 15 to 0)
0Fh
Reserved
Accesses assert the CAADDRx signal from the CAN peripheral (which asserts an Illegal Address error)
All unimplemented register bits are read as zero, writes have no effect. Register bits are initialized to zero, unless otherwise stated in the definition.
The mailboxes are situated in one 24 x 32 RAM with 16-bit access. It can be written to or read by the CPU or
the CAN. The CAN write or read access, as well as the CPU read access, needs one clock cycle. The CPU write
access needs two clock cycles. In these two clock cycles, the CAN performs a read-modify-write cycle and,
therefore, inserts one wait state for the CPU.
Address bit 0 of the address bus used when accessing the RAM decides if the lower (0) or the higher (1)
16-bit word of the 32-bit word is taken. The RAM location is determined by the upper bits 5 to 1 of the address
bus.
The enable signals for the RAM (EZ and GZ) are always active low.
Table 18 shows the mailbox locations in RAM. One half-word has 16 bits.
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