參數(shù)資料
型號(hào)： TMS320F243PGES
元件分類： 數(shù)字信號(hào)處理
英文描述： 16-Bit Digital Signal Processor
中文描述： 16位數(shù)字信號(hào)處理器
文件頁數(shù)： 12/116頁
文件大?。?/td> 1485K
代理商： TMS320F243PGES
TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999
12
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Terminal Functions - ’F243 PGE Package (Continued)
NAME
144
QFP
NO.
TYPE
RESET
STATE
DESCRIPTION
TEST SIGNALS (CONTINUED)
TRST
30
I
I
JTAG test reset with internal pulldown. TRST, when driven high, gives
the scan system control of the operations of the device. If this signal is
not connected or driven low, the device operates in its functional mode,
and the test reset signals are ignored.
EMU0
45
I/O
I
Emulator I/O pin 0 with internal pullup. When TRST is driven high, this
pin is used as an interrupt to or from the emulator system and is defined
as input/output through the JTAG scan.
EMU1/OFF
47
I/O
I
Emulator I/O pin 1 with internal pullup. When TRST is driven high, this
pin is used as an interrupt to or from the emulator system and is defined
as input/output through JTAG scan.
SUPPLY SIGNALS
14
15
36
37
40
70
VSSO
73
–
–
Digital logic and buffer ground reference
108
111
117
124
129
131
34
39
VDDO
72
Digital logic and buffer supply voltage
75
–
–
106
109
17
VDD
53
–
–
Digital logic supply voltage
125
16
VSS
32
Digital logic ground reference
51
127
–
–
I = input, O = output, Z = high impedance
The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is
an output, its level at reset is indicated.
§ In silicon revisions 2.0-TMX and 2.1-TMS, this pin is level-sensitive and can cause multiple interrupts when held low.
Data is in output mode when AVIS is enabled. At reset, the device comes up with AVIS mode enabled. The data bus is in output mode while AVIS
is enabled.
NOTE:
Bold, italicized pin names
indicate pin function after reset.
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