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| 型號： | TMS320F243PGES |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-Bit Digital Signal Processor |
| 中文描述： | 16位數(shù)字信號處理器 |
| 文件頁數(shù)： | 26/116頁 |
| 文件大小： | 1485K |
| 代理商： | TMS320F243PGES |
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TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999
26
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
digital I/O control registers
Table 9 lists the registers available in the digital I/O module. As with other ’F243/’F241 peripherals, the registers
are memory-mapped to the data space.
Table 9. Addresses of Digital I/O Control Registers
ADDRESS
REGISTER
NAME
7090h
OCRA
I/O mux control register A
7092h
OCRB
I/O mux control register B
7098h
PADATDIR
I/O port A data and direction register
709Ah
PBDATDIR
I/O port B data and direction register
709Ch
PCDATDIR
I/O port C data and direction register
709Eh
PDDATDIR
I/O port D data and direction register
device reset and interrupts
The TMS320x24x software-programmable interrupt structure supports flexible on-chip and external interrupt
configurations to meet real-time interrupt-driven application requirements. The ’F243/’F241 recognizes three
types of interrupt sources:
Reset
(hardware- or software-initiated) is unarbitrated by the CPU and takes immediate priority over any
other executing functions. All maskable interrupts are disabled until the reset service routine enables them.
The ’F243/’F241 devices have two sources of reset: an external reset pin and a watchdog timer timeout
(reset).
Hardware-generated interrupts
are requested by external pins or by on-chip peripherals. There are two
types:
–
External interruptsare generated by one of four external pins corresponding to the interrupts XINT1,
XINT2, PDPINT, and NMI. The first three can be masked both by dedicated enable bits and by the CPU’s
interrupt mask register (IMR), which can mask each maskable interrupt line at the DSP core. NMI, which
is not maskable, takes priority over peripheral interrupts and software-generated interrupts. It can be
locked out only by an already executing NMI or a reset.
–
Peripheral interrupts
are initiated internally by these on-chip peripheral modules: the event manager,
SPI, SCI, WD, CAN, and ADC. They can be masked both by enable bits for each event in each peripheral
and by the CPU’s IMR, which can mask each maskable interrupt line at the DSP core.
Software-generated interrupts
for the ’F243/’F241 devices include:
–
The INTR instruction.This instruction allows initialization of any ’F243/’F241 interrupt with software. Its
operand indicates the interrupt vector location to which the CPU branches. This instruction globally
disables maskable interrupts (sets the INTM bit to 1).
–
The NMI instruction.This instruction forces a branch to interrupt vector location 24h, the same location
used for the nonmaskable hardware interrupt NMI. NMI can be initiated by driving the NMI pin low or by
executing an NMI instruction. This instruction globally disables maskable interrupts.
–
The TRAP instruction.This instruction forces the CPU to branch to interrupt vector location 22h. The
TRAP instruction does notdisable maskable interrupts (INTM is not set to 1); therefore, when the CPU
branches to the interrupt service routine, that routine can be interrupted by the maskable hardware
interrupts.
–
An emulator trap. This interrupt can be generated with either an INTR instruction or a TRAP instruction.
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