參數(shù)資料
型號： TMP320C6413ZTSA500
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Fixed-Point Digital Signal Processors
中文描述： 定點數(shù)字信號處理器
文件頁數(shù)： 93/140頁
文件大?。?/td> 1958K
代理商： TMP320C6413ZTSA500
Peripheral Electrical Specifications
93
April 2004
Revised May 2005
SPRS247E
7
Peripheral Electrical Specifications
7.1
Input and Output Clocks
Table 7
1. Timing Requirements for External Crystal Oscillator Input (OSCIN and OSCOUT)
NO.
400
500
UNIT
MIN
12
MAX
1
f
OSC
Input oscillator frequency
30
MHz
The PLL multiplier factors (x5, x6, x7, x8, x9, x10, x11, x12, x16, x18, x19, x20, x21, x24) further limit the MIN and MAX values for CLKIN and
OSCIN. For more details on these limitations, see Table 4
1 and Table 4
2 of the
Clock PLL and Oscillator
section of this data sheet.
Table 7
2. Timing Requirements for CLKIN
§
(see Figure 7
1)
NO.
400
500
UNIT
PLL MULT MODE
MIN
10
0.45C
0.45C
x1 (BYPASS)
MIN
10
0.45C
0.45C
MAX
83.3
MAX
83.3
1
2
3
4
t
c(CLKIN)
t
w(CLKINH)
t
w(CLKINL)
t
t(CLKIN)
t
J(CLKIN)
Cycle time, CLKIN
Pulse duration, CLKIN high
Pulse duration, CLKIN low
Transition time, CLKIN
ns
ns
ns
ns
5
1
5
Period jitter, CLKIN
0.02C
0.02C
ns
The PLL multiplier factors (x5, x6, x7, x8, x9, x10, x11, x12, x16, x18, x19, x20, x21, x24) further limit the MIN and MAX values for CLKIN and
OSCIN. For more details on these limitations, see Table 4
1 and Table 4
2 of the
Clock PLL and Oscillator
section of this data sheet.
The reference points for the rise and fall transitions are measured at V
IL
MAX and V
IH
MIN.
§
C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
CLKIN
2
3
4
4
5
1
Figure 7
1. CLKIN Timing
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