參數(shù)資料
型號： TMP320C6413ZTSA500
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Fixed-Point Digital Signal Processors
中文描述： 定點數(shù)字信號處理器
文件頁數(shù)： 63/140頁
文件大?。?/td> 1958K
代理商： TMP320C6413ZTSA500
Terminal Functions
63
April 2004
Revised May 2005
SPRS247E
Table 3
9. Terminal Functions (Continued)
NAME
DESCRIPTION
IPD/
IPU
TYPE
NO.
HOST-PORT INTERFACE (HPI) (CONTINUED)
IPU
Host-port data pin 31 (
I/O/Z
)
IPU
Host-port data pin 30 (
I/O/Z
)
IPU
Host-port data pin 29 (
I/O/Z
) [default] or McASP1 mute input (
I
).
IPU
Host-port data pin 28 (
I/O/Z
) [default] or McASP1 mute output (
I/O/Z
).
Host-port data pin 27 (
I/O/Z
) [default] or McASP1 transmit high-frequency master clock
(
I/O/Z
).
HD31
HD30
HD29/AMUTEIN1
HD28/AMUTE1
Y8
Y11
W11
W10
I/O/Z
I/O/Z
I
I/O/Z
HD27/AHCLKX1
Y4
I/O/Z
IPU
HD26/AHCLKR1
AB4
I/O/Z
IPU
Host-port data pin 26 (
I/O/Z
) [default] or McASP1 receive high-frequency master clock
(
I/O/Z
).
HD25/ACLKR1
HD24/ACLKX1
AA9
AA4
I/O/Z
I/O/Z
IPU
IPU
Host-port data pin 25 (
I/O/Z
) [default] or McASP1 receive bit clock (
I/O/Z
).
Host-port data pin 24 (
I/O/Z
) [default] or McASP1 transmit bit clock (
I/O/Z
).
Host-port data pin 23 (
I/O/Z
) [default] or McASP1 receive frame sync or left/right clock
(LRCLK) (
I/O/Z
).
HD23/AFSR1
AB9
I/O/Z
IPU
HD22/AFSX1
AB5
I/O/Z
IPU
Host-port data pin 22 (
I/O/Z
) [default] or McASP1 transmit frame sync or left/right clock
(LRCLK) (
I/O/Z
).
HD21/AXR1[5]
HD20/AXR1[4]
HD19/AXR1[3]
HD18/AXR1[2]
HD17/AXR1[1]
HD16/AXR1[0]
HD15/GP0[15]
HD14/GP0[14]
HD13/GP0[13
]
HD12/GP0[12]
HD11/GP0[11]
HD10/GP0[10]
HD9/GP0[9]
HD8/GP0[8]
Y9
AB8
AA6
AB7
AA7
AB6
Y12
AA12
AB13
Y14
AB14
AA15
Y16
AB16
I/O/Z
IPU
Host port data [21:16] pin (
Host-port data [21:16] pin (
I/O/Z
) [default] or McASP1 TX/RX data pins [5:0] (
I/O/Z
).
I/O/Z
IPU
Host-port data [15:8] pins (
) [default] or General-purpose input/output (GP0) [15:8]
Host port data [15:8] pins (
I/O/Z
) [default] or General purpose input/output (GP0) [15:8]
pins (
I/O/Z
).
HD7
W12
Host-port data [7:0] pins (
Host port data [7:0] pins (
I/O/Z
)
HD6
AA13
Host Port bus width user configurable at device reset via a 1 k
pullup/
Host-Port bus width user-configurable at device reset via a 1-k
pulldown resistor on the HD5 pin (
I
):
HD5
Y13
HD4
AA14
I/O/Z
IPU
HD5 pin 0: HPI operates as an HPI16
HD5 pin = 0: HPI operates as an HPI16.
(HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins
are reserved pins in the high-impedance state.)
HD3
AB15
HD2
AA16
HD1
Y15
HD5 pin = 1: HPI operates as an HPI32.
HD0
W15
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog Signal
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k
IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
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