- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382648 > TMP320C6413ZTSA500 (Texas Instruments, Inc.) Fixed-Point Digital Signal Processors PDF資料下載
參數(shù)資料
| 型號(hào)： | TMP320C6413ZTSA500 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Fixed-Point Digital Signal Processors |
| 中文描述： | 定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 57/140頁(yè) |
| 文件大?。?/td> | 1958K |
| 代理商： | TMP320C6413ZTSA500 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)當(dāng)前第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)
Terminal Functions
57
April 2004
Revised May 2005
SPRS247E
Table 3
9. Terminal Functions (Continued)
NAME
NO.
TYPE
IPD/
IPU
DESCRIPTION
JTAG EMULATION (CONTINUED)
Emulation pin 2. Reserved for future use, leave unconnected.
Emulation pin 3. Reserved for future use, leave unconnected.
Emulation pin 4. Reserved for future use, leave unconnected.
Emulation pin 5. Reserved for future use, leave unconnected.
Emulation pin 6. Reserved for future use, leave unconnected.
Emulation pin 7. Reserved for future use, leave unconnected.
Emulation pin 8. Reserved for future use, leave unconnected.
Emulation pin 9. Reserved for future use, leave unconnected.
Emulation pin 10. Reserved for future use, leave unconnected.
Emulation pin 11. Reserved for future use, leave unconnected.
RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS
I
Device reset
I
IPD
Nonmaskable interrupt, edge-driven (rising edge)
EMU2
EMU3
EMU4
EMU5
EMU6
EMU7
EMU8
EMU9
EMU10
EMU11
R2
U2
R3
P2
R4
V2
V1
V3
W3
W2
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
RESET
NMI
C9
B9
GP0[7]/EXT_INT7
Y1
I/O/Z
IPU
General-purpose input/output (GPIO) pins (
I/O/Z
) or external interrupts (
input only
).
Th d f
l f
i GPIO
The default after reset setting is GPIO enabled as input-only.
When these pins function as External Interrupts [by selecting the corresponding
interrupt enable register bit (IER.[7:4])], they are edge-driven and the polarity can be
independently selected via the External Interrupt Polarity Register bits
(EXTPOL.[3:0]).
bl d
GP0[6]/EXT_INT6
C4
I/O/Z
IPU
p p
p
GP0[5]/EXT_INT5
B4
I/O/Z
IPU
GP0[4]/EXT_INT4
A4
I/O/Z
IPU
HD15/GP0[15]
HD14/GP0[14]
HD13/GP0[13
]
HD12/GP0[12]
HD11/GP0[11]
HD10/GP0[10]
HD9/GP0[9]
HD8/GP0[8]
GP0[3]
CLKOUT6/GP0[2]
§
CLKOUT4/GP0[1]
§
GP0[0]
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog Signal
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k
IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
Y12
AA12
AB13
Y14
AB14
AA15
Y16
AB16
B13
B3
A2
D13
I/O/Z
IPU
Host-port data pins (
I/O/Z
) [default] or General-purpose input/output (GP0) [15:8] pins
(
I/O/Z
)
p p
GP0 [3:0] pins (
I/O/Z
)
Clock output at 1/6 of the device speed (
O/Z
) [default] or this pin can be programmed as
GP0 2 i (
a GP0 2 pin (
I/O/Z
).
Clock output at 1/4 of the device speed (
O/Z
) [default] or this pin can be programmed as
a GP0 1 pin (
I/O/Z
).
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPD
IPU
IPU
IPD
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMX320F2810GHHA | DIGITAL SIGNAL PROCESSORS |
| TMX320F2810PBKA | DIGITAL SIGNAL PROCESSORS |
| TMP320F2810PBKA | DIGITAL SIGNAL PROCESSORS |
| TMX320F2810PBKAEP | Digital Signal Processors |
| TMP320F2810PBKAEP | Digital Signal Processors |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMP320C6414CGLZ300 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMP320C6414CGLZ5E0 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMP320C6414CGLZA300 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMP320C6414CGLZA5E0 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMP320C6414CZLZ300 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。