參數(shù)資料
型號： TMP320C6413ZTSA500
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Fixed-Point Digital Signal Processors
中文描述： 定點數(shù)字信號處理器
文件頁數(shù)： 126/140頁
文件大?。?/td> 1958K
代理商： TMP320C6413ZTSA500
Multichannel Buffered Serial Port (McBSP) Timing
126
April 2004
Revised May 2005
SPRS247E
Table 7
27. Switching Characteristics Over Recommended Operating Conditions for McBSP
(see Figure 7
36)
NO.
PARAMETER
400
500
UNIT
MIN
MAX
1
t
d(CKSH-CKRXH)
Delay time, CLKS high to CLKR/X high for internal CLKR/X generated
from CLKS input
1.4
10
ns
2
3
4
t
c(CKRX)
t
w(CKRX)
t
d(CKRH-FRV)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
Delay time, CLKR high to internal FSR valid
CLKR/X int
CLKR/X int
CLKR int
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
4P or 6.67
§#
ns
ns
ns
C
1
||
2.1
1.7
C + 1
||
3
3
9
4
9
9
t
d(CKXH-FXV)
Delay time CLKX high to internal FSX valid
Delay time, CLKX high to internal FSX valid
ns
1.7
3.9
12
t
dis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit
from CLKX high
ns
2
13
t
d(CKXH-DXV)
Delay time CLKX high to DX valid
Delay time, CLKX high to DX valid
3.9 + D1
2.0 + D1
4 + D2
9 + D2
ns
14
t
d(FXH-DXV)
Delay time, FSX high to DX valid
FSX int
2.3 + D1
5.6 + D2
ns
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
FSX ext
1.9 + D1
9 + D2
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
Minimum delay times also represent minimum output hold times.
§
Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times are based
on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
#
Use whichever value is greater.
||
C =
H or L
S =
sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H =
CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L =
CLKX low pulse width
= (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see footnote above).
Extra delay from CLKX high to DX valid
applies
only
to the first data bit of a device
, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 4P, D2 = 8P
Extra delay from FSX high to DX valid
applies
only
to the first data bit of a device
, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 4P, D2 = 8P
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