參數(shù)資料
型號: TMP320C6413ZTSA500
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Fixed-Point Digital Signal Processors
中文描述: 定點數(shù)字信號處理器
文件頁數(shù): 75/140頁
文件大小: 1958K
代理商: TMP320C6413ZTSA500
Host-Port Interface (HPI) Peripheral
75
April 2004
Revised May 2005
SPRS247E
4.2
Host-Port Interface (HPI) Peripheral
The TMS320C6413/C6410 device includes a user-configurable 16-bit or 32-bit Host-port interface
(HPI16/HPI32). On the C6413/C6410 device the HPI peripheral pins are muxed with the McASP1 and GP0
peripheral pins. By default, the HPI peripheral pin functions are enabled. For more detailed information on the
C6413/C6410 device pin muxing, see the Device Configurations section of this data sheet.
The HPI peripheral can be disabled or enabled at reset through the HPI enable function of the TOUT0/HPI_EN
pin. The HPI is enabled when the TOUT0/HPI_EN pin is sampled low at reset and it is disabled if the pin is
sample high at reset. The TOUT0/HPI_EN pin has an internal pulldown that enables the HPI by default.
However, the HPI can be disabled via an external pullup resistor or by having an external device such as an
FPGA/CPLD drive that pin high at reset. In the latter case, the external device should ensure it has stopped
driving this pin to avoid contention. The HPI enable function can only be set a reset and cannot be changed
via software.
The HD5 pin controls the HPI_WIDTH, allowing the user to configure the HPI as a 16-bit or 32-bit peripheral.
For more details on HPI peripheral configuration and the associated pins, see the Device Configurations
section of this data sheet.
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