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參數(shù)資料
| 型號(hào)： | TMC22X5YA |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit |
| 中文描述： | 多標(biāo)準(zhǔn)數(shù)字視頻解碼器三線自適應(yīng)梳狀解碼器系列，8 |
| 文件頁數(shù)： | 36/84頁 |
| 文件大小： | 417K |
| 代理商： | TMC22X5YA |
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TMC22x5yA
PRODUCT SPECIFICATION
36
REV. 1.0.0 2/4/03
Control Register De
fi
nitions
(continued)
Test Control (3D-3E)
7
6
5
4
3
2
1
0
TEST
Reg
3D-3E
Bit
7-0
Name
TEST
Description
Must be set to zero.
Auto increment stops at 3F
Test Control (3F)
7
6
5
4
3
2
1
0
VBIT20
PEDDIS
CCDEN
5
CCDEN
4
CCDEN
3
CCDEN
2
CCDEN
1
CCDEN
0
Reg
3F
Bit
7
Name
VBIT20
Description
VBIT20 enable.
When HIGH the V bit within embedded TRS words is
extended through line 20 for NTSC. When LOW, this V bit is HIGH up to line
16 for NTSC. The PAL operation is unaffected by this register bit.
Pedestal disable.
When HIGH, pedestal is not removed from lines with
LID = 00 to 06, lines 0 through 16
Closed caption data enable 5.
When HIGH, enables NTSC line 21 field 0
or PAL line 22 field 0 to be passed ‘FLAT’, through the decoder, on the
luminance channel and the pedestal removal will be disabled.
Closed caption data enable 4.
When HIGH, enables NTSC line 22 field 0
or PAL line 23 field 0 to be passed ‘FLAT’, through the decoder, on the
luminance channel and the pedestal removal will be disabled.
Closed caption data enable 3.
When HIGH, enables NTSC line 23 field 0
or PAL line 24 field 0 to be passed ‘FLAT’, through the decoder, on the
luminance channel and the pedestal removal will be disabled.
Closed caption data enable 2.
When HIGH, enables NTSC line 283 field 1
or PAL line 334 field 1 to be passed ‘FLAT’, through the decoder, on the
luminance channel and the pedestal removal will be disabled.
Closed caption data enable 1.
When HIGH, enables NTSC line 284 field 1
or PAL line 335 field 1 to be passed ‘FLAT’, through the decoder, on the
luminance channel and the pedestal removal will be disabled.
Closed caption data enable 0.
When HIGH, enables NTSC line 285 field 1
or PAL line 336 field 1 to be passed ‘FLAT’, through the decoder, on the
luminance channel and the pedestal removal will be disabled.
3F
6
PEDDIS
3F
5
CCDEN
5
3F
4
CCDEN
4
3F
3
CCDEN
3
3F
2
CCDEN
2
3F
1
CCDEN
1
3F
0
CCDEN
0
Status - Read Only (40)
7
6
5
4
3
2
1
0
DDSPH
Reg
40
Bit
7-0
Name
DDSPH
Description
DDS phase, 8 msbs.
The top 8 bits of the sine data generated in the internal
DDS.
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