參數(shù)資料
型號: TMC22X5YA
廠商: Fairchild Semiconductor Corporation
英文描述: Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit
中文描述: 多標(biāo)準(zhǔn)數(shù)字視頻解碼器三線自適應(yīng)梳狀解碼器系列,8
文件頁數(shù): 34/84頁
文件大?。?/td> 417K
代理商: TMC22X5YA
TMC22x5yA
PRODUCT SPECIFICATION
34
REV. 1.0.0 2/4/03
Control Register De
fi
nitions
(continued)
Registers 34-3C are Read-Only
Video Measurement (33)
7
6
5
4
3
2
1
0
Reserved
FG
LG
8
PG
10
PG
9
PG
8
Reg
33
33
33
33
Bit
7
6-4
3
2-0
Name
Reserved
FG
LG
8
PG
10-8
Description
Reserved.
Field grab number.
Field grab number
Msb of line grab.
msb of line grab
Pixel grab, 3 msbs.
3 msbs of pixel grab
Register
(34)
7
6
5
4
3
2
1
0
GY
9
GY
8
GY
7
GY
6
GY
5
GY
4
GY
3
GY
2
Reg
34
Bit
7-0
Name
GY
9-2
Description
G/Y grab, 8 msbs.
Top 8 bits of the "grabbed" G/Y data
Register
(35)
7
6
5
4
3
2
1
0
BU
9
BU
8
BU
7
BU
6
BU
5
BU
4
BU
3
BU
2
Reg
35
Bit
7-0
Name
BU
9-2
Description
B/U grab, 8 msbs.
Top 8 bits of the "grabbed" B/U data
Register
(36)
7
6
5
4
3
2
1
0
RV
9
RV
8
RV
7
RV
6
RV
5
RV
4
RV
3
RV
2
Reg
36
Bit
7-0
Name
RV
9-2
Description
R/V grab, 8 msbs.
Top 8 bits of the "grabbed" R/V data
Register
(37)
7
6
5
4
3
2
1
0
Reserved
GY
1
GY
0
BU
1
BU
0
RV
1
RV
0
Reg
37
37
37
37
Bit
7-6
5-4
3-2
1-0
Name
Reserved
GY
1-0
BU
1-0
RV
1-0
Description
Reserved.
G/Y grab, 2 lsbs.
Bottom two bits of G/Y data
B/U grab, 2 lsbs.
Bottom two bits of B/U data
R/V grab, 2 lsbs.
Bottom two bits of R/V data
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