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參數(shù)資料
| 型號(hào)： | TMC22X5YA |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit |
| 中文描述： | 多標(biāo)準(zhǔn)數(shù)字視頻解碼器三線自適應(yīng)梳狀解碼器系列，8 |
| 文件頁(yè)數(shù)： | 32/84頁(yè) |
| 文件大小： | 417K |
| 代理商： | TMC22X5YA |
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TMC22x5yA
PRODUCT SPECIFICATION
32
REV. 1.0.0 2/4/03
Control Register De
fi
nitions
(continued)
Buffered register set 1 (2D)
Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
Reserved
YOFF1
8
SG1
9
SG1
8
Reg
2D
2D
2D
Bit
7-3
2
1-0
Name
Reserved
YOFF1
8
SG1
9,8
Description
Reserved, set to zero.
Y offset, msb.
msb of YOFF
Msync gain, 2 msbs.
Top 2 bits of mixed sync scalar
msb = 2
Buffered register set 1 (2E)
Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
SYSPH1
6
SYSPH1
5
SYSPH1
4
SYSPH1
3
SYSPH1
2
SYSPH1
1
SYSPH1
0
VAXISO
Reg
2E
2E
Bit
7-1
0
Name
SYSPH1
6-0
VAXIS1
Description
7 lsbs of phase offset.
Bottom 7 bits of the 15 bit system phase offset
V axis flip.
Flips the sign of the V axis when HIGH.
Buffered register set 1 (2F)
Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
SYSPH1
14
SYSPH1
13
SYSPH1
12
SYSPH1
11
SYSPH1
10
SYSPH1
9
SYSPH1
8
SYSPH1
7
Reg
2F
Bit
7-0
Name
SYSPH114-7
Description
8 msbs of phase offset.
Top 8 bits of 15 bit system phase offset.
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