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參數資料
| 型號： | TMC22051 |
| 廠商： | RAYTHEON SEMICONDUCTOR |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | 8-Bit Digital Video Decoder(8位數字視頻譯碼器) |
| 中文描述： | COLOR SIGNAL DECODER |
| 文件頁數： | 64/84頁 |
| 文件大?。?/td> | 414K |
| 代理商： | TMC22051 |
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TMC22x5y
PRODUCT SPECIFICATION
64
P
VINDO Operation
The VINDO circuit uses the line idents on LID
4-0
, and the
blanking signals to control the comb filter output and the
blanking of the YUV data in the output matrix during the
vertical blanking period.
The vertical window VINDO starts on the first line after the
last equalizing pulse, at LID
4-0
= 02. The VINDO stays
HIGH from this line until the VINDO count = VINDO
4-0
, or
the VBLK signal goes HIGH, at which time the VINDO goes
LOW. While the VINDO is HIGH the decoder operation is
controlled by VDIV, and during the time the VINDO and
VBLK are LOW the decoder operation is controlled by
VDOV.
Table 22. PAL VINDO operation
NTSC VINDO operation
Video Measurement
The TMC22x5y supports a comprehensive set of video
measurement techniques to aid the user in setting up the
gain, phase, etc. of the decoder and in tracking down system
errors.
Pixel Grab
The pixel grab allows the user to grab one pixel every line,
or one pixel out of the four field sequence in NTSC or the 8
field sequence in PAL, under software control. The SET pin
can also be used to produce the pixel grab pulse if SET
2-0
=
110 and PGEXT is set HIGH.
The 10 bit G/Y, B/U, R/V outputs are stored in one set of
four 8 bit registers in the FORMAT block, while the 10 bit
luma and mixed sync data and the 10 bit demodulated U and
V color difference signals are stored in a set of five 8 bit
registers in the GRAB circuit block. The pixel grab signal,
PIXEL, whether internally or externally generated, is inter-
nally delayed to ensure that the all the grabbed data are from
the same pixel relative to the line sync pulse. The PIXEL
signal is equal to PGRAB or the logical AND of PGRAB
with FGRAB and LGRAB, and is controlled by the LPGEN,
PGEN, and PGEXT register bits.
The luma and mixed sync signals are multiplexed on the
YMS data bus and the U and V signals are multiplexed on
the UV data bus, at the PXCK clock rate. The pixel grab
signal accommodates for this when grabbing these
components.
An example of the pixel grab feature, is grabbing a pixel in
the center of the burst period allowing the user to check the
burst height by reading the magnitude of the demodulated U
and V components. This allows the user to compensate for
any chrominance gain errors in the output matrix.
LID
4-0
00 - 01
02 - 0A
02 - 0A
02 - 0A
02 - 0A
0B - 17
VINDO
x
1
1
0
0
x
VDIV
x
0
1
x
x
x
VDOV
x
x
x
0
1
x
Y
C
normal
simple
flat
black
simple
normal
normal
simple
black
black
black
normal
LID
4-0
00 - 02
03 - 06
03 - 06
03 - 06
03 - 06
07 - 17
VINDO
x
1
1
0
0
x
VDIV
x
0
1
x
x
x
VDOV
x
x
x
0
1
x
Y
C
normal
simple
flat
black
simple
normal
normal
simple
black
black
black
normal
Figure 31. Pixel Grab Locations
Video A
Video B
Pixel
Luma and
Chroma
Separation
C Data
C Data
dT
dT
Luma
Proc
LPF
Y
MS
U
V
YMS
UV
Output
Matrix
Output
Formatter
and Buffer
G/Y
B/U
R/V
LPF
U Data
register 3A/3C
register 3A/3C
register 3A/3C
register 3A/3C
register 34/37
register 35/37
register 36/37
V Data
Y Data
MS Data
G/Y
B/U
RV
Chroma
Demodulation
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