參數(shù)資料
型號(hào)： TMC22051
廠商： RAYTHEON SEMICONDUCTOR
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： 8-Bit Digital Video Decoder(8位數(shù)字視頻譯碼器)
中文描述： COLOR SIGNAL DECODER
文件頁(yè)數(shù)： 57/84頁(yè)
文件大小： 414K
代理商： TMC22051
PRODUCT SPECIFICATION
TMC22x5y
57
P
Simple Luma Color Correction
If the YBAL register bit is set HIGH, and the luma data
reaches or exceeds the luma limits, there should be no C
B
C
R
or UV data at that time; therefore the color data are set to
ZERO. If YBAL is set LOW then the C
B
C
R
/UV data are
unaffected by the luma data.
C
B
C
R
MSB Inversion
The msb of the C
B
C
R
data can be inverted by setting the
MSBO register bit HIGH. As this would affect the chroma
blanking level, this circuit appears at the output of the
MATRIX circuit.
Output Rounding
For compatibility with 8 bit systems, the output of the matrix
can be rounded to 8 bits by setting the RND8 register bit
HIGH.
Output Formats
RGB Outputs
The RGB data are simply passed through to the decoder out-
put. When the DRSEN register bit is HIGH the DRS data are
inserted into the green data path only.
YUV Outputs
The YUV data are simply passed through to the decoder out-
put. When the DRSEN register bit is HIGH the DRS data are
inserted into the luminance data path only.
YC
B
C
R
Outputs
The YC
B
C
R
data can be output in 3 ways, depending upon
the CDEC, F422, and YUVT register bits. These output
modes are summarized in .
When CDEC is HIGH and F422 is HIGH, the G/Y output is
set to 64 and the B/U output is set to 512 between the EAV
TRS data word and the first preamble word of the SAV TRS,
i.e. during the digital horizontal blanking period. When
YUVT is HIGH, R/V is set to 512, 64, 512, 64, etc., starting
after the EAV TRS data word and finishing before the SAV
preamble.
Decimating C
B
C
R
Data
Whenever the CDEC register bit is set HIGH the B/U and
R/V data are simply sample dropped, with respect to
CBSEL, to produce the multiplexed C
B
C
R
data stream at the
PCK clock rate. If the input was initially D1 then the
dropped samples will be the interpolated samples produced
by the chroma interpolation filter. If however the C
B
C
R
data
are simply weighted UV data then the sample dropped
demodulated color difference signals (UV) will alias around
0.25 of the normalized sample frequency.
Multiplexed YC
B
C
R
Output (TRS Words
Inserted)
When both the CDEC and YUVT register bits are HIGH the
Y, C
B
, and C
R
component data are multiplexed into a single
27MHz (PXCK) data stream with embedded TRS words.
The TRS words are generated based on the HSYNC or
VSYNC pulses provided to the decoder, and the internally
derived horizontal blanking (HBLK), vertical blanking
(VBLK), and the field flag (FLD). This mode of operation is
only available if a line locked PXCK clock, at 27MHz, is
provided. The TRS words will be generated with respect to
the HSYNC\ signal as per the ANSI/SMPTE 125M-1992
and CCIR 656 specifications.
YC Outputs
The YC data are passed through to the decoder output. When
the DRSEN register bit is HIGH the DRS data are inserted
into the luminance data path only. The luminance appears on
G/Y, chrominance is on B/U and the R/V output is set to
zero, by setting the V_scalar to zero.
The LDV Clock
The decoder can accept clocks at either the pixel clock rate
(PCK) or at twice the pixel clock rate (PXCK). In the cases
where the clock provided is PXCK, for example the genlock
mode, the output data still needs to be at the PCK clock rate.
To aid in the design of external circuitry a LDV clock is pro-
vided if the LDVIO register bit is LOW, if LDVIO is HIGH
then the LDV pin becomes an input for an external clock.
If an external LDV clock is employed the user must ensure
that the rising edge of the external LDV meets the specified
setup and hold times relative to the input CLOCK pin. The
selection of which clock to use on the decoder output is set
by the OPSEL register bit. When OPSEL is set LOW the
output is clocked at the same rate as the clock on the
CLOCK pin, and when OPSEL is set HIGH the output is
clocked by the internal or external clock on the LDV pin.
Table 14. Output Format
CDEC
0
1
1
1
YUVT
x
0
0
1
F422
x
0
1
x
G/Y
G or Y
Y
Y
Y
B/U
B or C
B
C
B
C
B
C
R
C
B
C
R
R/V
Comments
R or C
R
C
R
0
D1 data
[4:4:4] data
[4:2:2] data
[4:2:2] data
[4:2:2] data & D1 output
相關(guān)PDF資料
PDF描述
TMC22052 8-Bit Digital Video Decoder(8位數(shù)字視頻譯碼器)
TMC22053 8-Bit Digital Video Decoder(8位數(shù)字視頻譯碼器)
TMC22152 8-Bit/10-Bit Digital Video Decoder(8位/10位數(shù)字視頻譯碼器)
TMC22153 8-Bit/10-Bit Digital Video Decoder(8位/10位數(shù)字視頻譯碼器)
TMC222 MotionControl Integrated Circuit
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMC22051 WAF 制造商:Fairchild Semiconductor Corporation 功能描述:
TMC22051AKHC 功能描述:多媒體雜項(xiàng) RoHS:否 制造商:Texas Instruments 類型: 通道數(shù)量: 轉(zhuǎn)換速率:540 Mbps 分辨率: 封裝 / 箱體:SOIC-16 封裝:Tube
TMC22052AKHC 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit
TMC22053AKHC 制造商:Rochester Electronics LLC 功能描述:- Bulk
TMC22053KHC 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Fairchild Semiconductor Corporation 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*