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參數(shù)資料
| 型號： | TLV320DAC3101IRHBR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | DAC WITH PROGRAMMABLE PLL, PQCC32 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, QFN-32 |
| 文件頁數(shù)： | 53/100頁 |
| 文件大?。?/td> | 1281K |
| 代理商： | TLV320DAC3101IRHBR |
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SLAS666 – JANUARY 2010
www.ti.com
5.7
Digital Audio and Control Interface
5.7.1
Digital Audio Interface
Audio data is transferred between the host processor and the TLV320DAC3101 via the digital audio data
serial interface, or audio bus. The audio bus on this device is very flexible, including left- or right-justified
data options, support for I2S or DSP protocols, programmable data length options, a TDM mode for
multichannel operation, very flexible master/slave configurability for each bus-clock line, and the ability to
communicate with multiple devices within a system directly.
The audio bus of the TLV320DAC3101 can be configured for left- or right-justified, I2S, DSP, or TDM
modes of operation, where communication with standard telephony interfaces is supported within the TDM
mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by
configuring page 0 / register 27, bits D5–D4. In addition, the word clock and bit clock can be
independently configured in either master or slave mode for flexible connectivity to a wide variety of
processors. The word clock is used to define the beginning of a frame, and may be programmed as either
a pulse or a square-wave signal. The frequency of this clock corresponds to the DAC sampling frequency.
The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in master
mode, this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider
in page 0 / register 30 (see Figure 5-20). The number of bit-clock pulses in a frame may need adjustment
to accommodate various word lengths as well as to support the case when multiple TLV320DAC3101s
may share the same audio bus.
The TLV320DAC3101 also includes a feature to offset the position of start of data transfer with respect to
the word clock. This offset can be controlled in terms of number of bit clocks and can be programmed in
page 0 / register 28.
The TLV320DAC3101 also has the feature of inverting the polarity of the bit clock used for transferring the
audio data as compared to the default clock polarity used. This feature can be used independently of the
mode of audio interface chosen. This can be configured via page 0 / register 29, bit D3.
By default, when the word clocks and bit clocks are generated by the TLV320DAC3101, these clocks are
active only when the DAC is powered up within the device. This is done to save power. However, it also
supports a feature when both the word clocks and bit clocks can be active even when the codec in the
device is powered down. This is useful when using the TDM mode with multiple codecs on the same bus,
or when word clocks or bit clocks are used in the system as general-purpose clocks.
5.7.1.1
Right-Justified Mode
The audio interface of the TLV320DAC3101 can be put into the right-justified mode by programming
page 0 / register 27, bits D7–D6 = 10. In right-justified mode, the LSB of the left channel is valid on the
rising edge of the bit clock preceding the falling edge of the word clock. Similarly, the LSB of the right
channel is valid on the rising edge of the bit clock preceding the rising edge of the word clock.
56
APPLICATION INFORMATION
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320DAC3101
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