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參數資料
| 型號： | TLV320DAC3101IRHBR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | DAC WITH PROGRAMMABLE PLL, PQCC32 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, QFN-32 |
| 文件頁數： | 50/100頁 |
| 文件大?。?/td> | 1281K |
| 代理商： | TLV320DAC3101IRHBR |
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÷N
BCLK
DAC_CLK
DAC_MOD_CLK
BDIV_CLKIN
N = 1, 2, ..., 127, 128
B0362-01
www.ti.com
SLAS666 – JANUARY 2010
The DAC modulator is clocked by DAC_MOD_CLK. For proper power-up operation of the DAC channel,
DAC_MOD_CLK must be enabled by configuring the NDAC and MDAC clock dividers (page 0 /
register 11, bit D7 = 1 and page 0 / register 12, bit D7 = 1). When the DAC channel is powered down, the
device internally initiates a power-down sequence for proper shutdown. During this shutdown sequence,
the NDAC and MDAC dividers must not be powered down, or else a proper low-power shutdown may not
take place. The user can read back the power-status flag at page 0 / register 37, bit D7 and page 0 /
register 37, bit D3. When both the flags indicate power-down, the MDAC divider may be powered down,
followed by the NDAC divider.
In general, for proper operation, all the root clock dividers should be powered down only after the child
clock dividers have been powered down.
The TLV320DAC3101 also has options for routing some of the internal clocks to the GPIO1 pin to be used
as general-purpose clocks in the system. The feature is shown in Figure 5-22.
Figure 5-21. BCLK Output Options
In the mode when the TLV320DAC3101 is configured to drive the BCLK pin (page 0 / register 27,
bit D3 = 1), it can be driven as the divided value of BDIV_CLKIN. The division value can be programmed
in page 0 / register 30, bits D6–D0 from 1 to 128. BDIV_CLKIN can itself be configured to be one of
DAC_CLK (DAC processing clock), DAC_MOD_CLK by configuring the BDIV_CLKIN multiplexer in page
0 / register 29, bits D1–D0.
Additionally, a general-purpose clock can be driven out on GPIO1. This clock can be a divided-down
version of CDIV_CLKIN. The value of this clock divider can be programmed from 1 to 128 by writing to
page 0 / register 26, bits D6–D0. CDIV_CLKIN can itself be programmed as one of the clocks among the
list shown in Figure 5-22. This can be controlled by programming the multiplexer in page 0 / register 25,
bits D2–D0.
Copyright 2010, Texas Instruments Incorporated
APPLICATION INFORMATION
53
Product Folder Link(s): TLV320DAC3101
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| TLV320DAC3101IRHBT | 功能描述:音頻數/模轉換器 IC Low-Pwr audio DAC RoHS:否 制造商:Texas Instruments 轉換器數量: 分辨率:16 bit 接口類型:I2S, UBS 轉換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| TLV320DAC3120 | 制造商:TI 制造商全稱:Texas Instruments 功能描述: |
| TLV320DAC3120_10 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Low-Power Mono Audio DAC With Embedded miniDSP and Mono Class-D Speaker Amplifier |
| TLV320DAC3120EVM-U | 功能描述:音頻 IC 開發(fā)工具 TLV320DAC3120EVM-U Eval Mod RoHS:否 制造商:Texas Instruments 產品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| TLV320DAC3120IRHBR | 功能描述:音頻數/模轉換器 IC Lo-Pwr Audio DAC w/ Audio Proc RoHS:否 制造商:Texas Instruments 轉換器數量: 分辨率:16 bit 接口類型:I2S, UBS 轉換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
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