參數(shù)資料
型號(hào)： TLV320AIC23BGQER
廠商： Texas Instruments, Inc.
元件分類(lèi)： Codec
英文描述： STEREO AUDIO CODEC 8 TO 96 KHZ WITH INTEGRATED HEADPHONE AMPLIFIER
中文描述： 立體聲音頻編解碼8至96與集成耳機(jī)放大器KHZ可
文件頁(yè)數(shù)： 27/50頁(yè)
文件大?。?/td> 499K
代理商： TLV320AIC23BGQER
37
This minimizes audible clicks as the volume is changed or the device is muted. This circuit has no time-out, so, if only
dc levels are being applied to the gain stage input of more than 20 mV, the gain is not updated.
The gain is independently programmable on the left and right channels. Both channels can be locked to the same
value by setting the RLS and LRS bits (see Section 3.1.3).
3.2.5
The TLV320AIC23B includes a bypass mode in which the analog line inputs are directly routed to the analog line
outputs, bypassing the ADC and DAC. This is enabled by selecting the bypass bit in the analog audio path control
register[see Section 3.1.3).
For a true bypass mode, the output from the DAC and the sidetone should be disabled. The line input and headphone
output volume controls and mutes are still operational in bypass mode. Therefore the line inputs, DAC output, and
microphone input can be summed together. The maximum signal at any point in the bypass path must be no greater
than 1.0V
rms
at AV
DD
=3.3V to avoid clipping and distortion. This amplitude tracks linearly with AV
DD
.
3.2.6
Sidetone Insertion
The TLV320AIC23B has a sidetone insertion made where the microphone input is routed to the line and headphone
outputs. This is useful for telephony and headset applications. The attenuation of the sidetone signal may be set to
6 dB, 9 dB, 12 dB, 15 dB, or 0dB, by software selection (see Section 3.1.3). If this mode is used to sum the
microphone input with the DAC output and line inputs, care must be taken not to exceed signal level to avoid clipping
and distortion.
Analog Bypass Mode
3.3
Digital Audio Interface
3.3.1
The TLV320AIC23B supports four audio-interface modes.
Right justified
Left justified
I
2
S mode
DSP mode
The four modes are MSB first and operate with a variable word width between 16 to 32 bits (except right-justified
mode, which does not support 32 bits).
The digital audio interface consists of clock signal BCLK, data signals DIN and DOUT, and synchronization signals
LRCIN and LRCOUT. BCLK is an output in master mode and an input in slave mode.
Digital Audio-Interface Modes
3.3.1.1 Right-Justified Mode
In right-justified mode, the LSB is available on the rising edge of BCLK, preceding a falling edge on LRCIN or LRCOUT
(see Figure 3-5).
LRCIN/
LRCOUT
BCLK
DIN/
DOUT
n
n1
0
1
n1
n
1/fs
Left Channel
Right Channel
1
0
0
MSB
LSB
Figure 35. Right-Justified Mode Timing
3.3.1.2 Left-Justified Mode
In left-justified mode, the MSB is available on the rising edge of BCLK, following a rising edge on LRCIN or LRCOUT
(see Figure 3-6)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TLV320AIC23BIGQE 功能描述:接口—CODEC Lo-Pwr Highly Integrated Codec RoHS:否 制造商:Texas Instruments 類(lèi)型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類(lèi)型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TLV320AIC23BIGQER 功能描述:接口—CODEC L-P Stereo CODEC with HP Amplifier RoHS:否 制造商:Texas Instruments 類(lèi)型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類(lèi)型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TLV320AIC23BIPW 功能描述:接口—CODEC Lo-Pwr Highly Integrated Codec RoHS:否 制造商:Texas Instruments 類(lèi)型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類(lèi)型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TLV320AIC23BIPW 制造商:Texas Instruments 功能描述:IC CODEC AUDIO SMD TSSOP28 320
TLV320AIC23BIPWG4 功能描述:接口—CODEC Lo-Pwr Highly Integrated Codec RoHS:否 制造商:Texas Instruments 類(lèi)型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類(lèi)型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
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